PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 24
PC87393VJG
Manufacturer Part Number
PC87393VJG
Description
IC, SUPER I/O DEVICE, TQFP-100
Manufacturer
National Semiconductor
Specifications of PC87393VJG
Data Rate
2Mbps
Supply Voltage Range
3V to 3.6V
Logic Case Style
TQFP
No. Of Pins
100
Operating Temperature Range
0°C to +70°C
Termination Type
SMD
Transceiver Type
Interface
Rohs Compliant
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PC87393VJG
Manufacturer:
NS/国半
Quantity:
20 000
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1.0 Signal/Pin Connection and Description
1.6 INTERNAL PULL-UP AND PULL-DOWN RESISTORS
The signals listed in Table 4 can optionally support internal pull-up (PU) and/or pull-down (PD) resistors. See Section 9.3 for
the values of each resistor type.
XIOWR
XD7-0
XA19-0
XCS1-0
XSTB2-0
XRDY
PIRQA-D
Signal
82, 73
96, 97,
98, 99,
100, 1,
2, 3
74-95
73, 72
87, 90,
91
72, 35
87-84
Pin/s
I/O Buffer Type Power Well
I/O
O
O
O
O
I
I
JOYABTN0
JOYABTN1
JOYBBTN0
JOYBBTN1
GPIO00-07
GPIO10-17
GPIO20-27
GPIO30-37
MDRX
BADDR
TEST
IN
Signal
TS
IN
IN
O
O
O
O
3/6
3/6
3/6
3/6
/O
Table 4. Internal Pull-Up and Pull-Down Resistors
TS
TS
Musical Instrument Digital Interface (MIDI) Port
3/6
Game Port (GMP) (PC87393 and PC87393F)
General-Purpose Input/Output (GPIO) Ports
(PC87392, PC87393 and PC87393F)
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
(PC87393 and PC87393F)
Pin/s
Strap Configuration
I/O Write. Active (low) level indicates I/O write cycle on the X-Bus
Extension. This signal is for devices that require separate
read/write inputs for memory and I/O.
Data Bus
Address Bus
Chip Select. These signals control the selection of up to two
chips residing on the X-Bus Extension.
Assert Strobe. These signals control the selection of up to three
external latch devices for X-Bus Latched Address Mode
transactions.
I/O Ready. This signal indicates to the PC87393 to extend the
access cycles.
Parallel Interrupt. Convert parallel interrupts into serial interrupts
by means of the Interrupt Serializer (The interrupt number
associated with each signal is a part of the system configuration.)
24
(Continued)
Type
PU
PU
PU
PU
PU
PU
PU
PU
PU
PD
PD
25
25
25
25
25
25
25
25
25
40
15
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Strap
Strap
Comments
Description
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