PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 62
PC87393VJG
Manufacturer Part Number
PC87393VJG
Description
IC, SUPER I/O DEVICE, TQFP-100
Manufacturer
National Semiconductor
Specifications of PC87393VJG
Data Rate
2Mbps
Supply Voltage Range
3V to 3.6V
Logic Case Style
TQFP
No. Of Pins
100
Operating Temperature Range
0°C to +70°C
Termination Type
SMD
Transceiver Type
Interface
Rohs Compliant
No
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
PC87393VJG
Manufacturer:
NS/国半
Quantity:
20 000
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2.0 Device Architecture and Configuration
Bit
Name
Reset
2.17 GAME PORT (GMP) CONFIGURATION
This section applies to the PC87393 and PC87393F only.
2.17.1 Logical Device 11 (GMP) Configuration
Table 26 lists the configuration registers which affect the Game Port. Only the last register (F0h) is described here. See Sec-
tions 2.2.3 and 2.2.4 for a detailed description of the others.
2.17.2 Game Port Configuration Register
This register is reset by hardware to 00h.
Location:
Type:
7-4
Bit
3
2
1
0
Index
30h
60h
61h
70h
71h
74h
75h
F0h
Reserved
GMP Enhanced Mode Enable. See Usage Hints below.
0: Disabled (default)
1: Enabled
Internal Pull-Up Enable. When the GMP functions are selected, this bit controls the internal pull-up resistor on
pins 96 (GPIO07/JOYABTN0), 3 (GPIO00/JOYABTN1), 97 (GPIO06/JOYBBTN0) and 2 (GPIO01/JOYBBTN1) or
pins 74 (GPIO17/JOYABTN0), 81 (GPIO10/JOYABTN1), 75 (GPIO16/JOYBBTN0), 80 (GPIO11/JOYBBTN1).
0: Disabled (default)
1: Enabled
Reserved
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disabled (default)
1: Enabled
Activate. When bit 0 is cleared, the registers of this logical device are not
accessible.
Base Address MSB register
Base Address LSB register.
Interrupt Number and Wake-Up on IRQ Enable register.
Interrupt Type. Bit 1 is read/write. Other bits are read only.
Report no DMA assignment
Report no DMA assignment
Game Port Configuration register
Index F0h
R/W
7
0
6
0
Configuration Register or Action
Reserved
Table 26. GMP Configuration Registers
5
0
Description
62
4
0
(Continued)
Mode Enable
Enhanced
GMP
3
0
Internal
Pull-Up
Enable
2
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
Reserved
1
0
Reset
TRI-STATE
00h
02h
01h
00h
03h
04h
04h
00h
Control
0
0
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