HSP50210JC-52 Intersil, HSP50210JC-52 Datasheet - Page 33

• Manufacturer Part Number: HSP50210JC-52
• Description: Digital Costas Loop 84-Pin PLCC
• Manufacturer: Intersil

Specifications of HSP50210JC-52

• Package: 84PLCC
• Power Supply Type: Analog
• Typical Supply Current: 225 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

POSITION
POSITION
POSITION
30-28
27-24
23-16
31-8
15-8
31-8
BIT
BIT
BIT
7-0
7-0
7-6
31
Not Used
Power Threshold
Enable AGC
AGC Loop Gain
Exponent (E)
AGC Loop Gain
Mantissa (M)
AGC Threshold
AGC Upper Limit
AGC Lower Limit
Not Used
Reserved
FUNCTION
FUNCTION
FUNCTION
33
TABLE 18. CARRIER PHASE ERROR DETECTOR CONTROL REGISTER
TABLE 16. POWER DETECT THRESHOLD CONTROL REGISTER
TABLE 17. AGC LOOP PARAMETERS CONTROL REGISTER
The upper 8 bits of the AGC Accumulator set the AGC gain. The value programmed here sets upper limit
No programming required.
The THRESH output is driven low when the magnitude output of the Cartesian-to-Polar Converter
exceeds the threshold programmed here. The threshold is represented as an 8-bit fractional unsigned
value with the following format:
2
Using this format, the possible range of threshold values is between 0 to 1.9961. Bit position 7 is the MSB.
0 = Gain error enabled to AGC Loop Filter.
1 = Gain error into AGC Loop Filter set to zero.
These bits set the loop gain exponent as given by:
AGC Loop Gain Exponent = 2
where EEE corresponds to the 3-bit binary value programmed here. Thus, a gain range from 2
may be achieved for EEE = 000 to 111 Binary. Bit position 30 is the MSB. See Table 3 on page 11.
The loop gain mantissa is represented as a 4-bit unsigned value with the following format:
AGC Loop Gain Mantissa = 0. 2
This format provides a mantissa range from 0.0 to 0.9375 for mantissa settings from 0000 to 1111 Binary.
Bit position 27 is the MSB. Mantissa resolution = 0.0625. See Table 2 on page 11.
The AGC gain error is generated by subtracting the threshold value programmed here from the
magnitude value out of the Cartesian-to-Polar Converter. The binary format for the AGC Threshold is the
same as that for the Power Threshold given in Table 15 on page 32.
for AGC gain by specifying a limit for the upper 8 bits of the AGC accumulator. If the accumulated sum
exceeds the upper limit, the accumulator is loaded with the limit. These bits are packed as eemmmmmm
where the e’s correspond to the exponent bits and the m’s correspond to the mantissa bits of Equation 8
(see also Figure 8). Bit position 15 is the MSB. By setting the AGC upper and lower limits to the same value,
the AGC can be set to a fixed gain.
The value programmed here sets the lower limit for the upper 8 bits of the AGC accumulator in a manner
similar to that described for the upper limit. If the accumulated sum falls below the lower limit, the
accumulator is loaded with the limit. The format for these bits is as described for the upper limit. By setting
the AGC upper and lower limits to the same value, the AGC can be set to a fixed gain.
No programming required.
Reserved. Set to 0 for proper operation.
0
. 2
-1
2
-2
2
-3
2
DESTINATION ADDRESS = 1
DESTINATION ADDRESS = 2
DESTINATION ADDRESS = 3
-4
2
-5
1.1453 (42h)
0.8108 (67h)
0.5740 (49h)
0.4064 (34h)
0.2877 (24h)
2
HSP50210
-6
AGC THRESHOLD
2
-7
.
VALUE
-(7 + EEE)
-1
2
-2
2
-3
2
-4
; 0.MMMM.
DESCRIPTION
DESCRIPTION
DESCRIPTION
RESULTING OUTPUT
LEVEL (dBFS)
-12
-3
-6
-9
0
-7
July 2, 2008
to 2
FN3652.5
-14