MT90401AB Zarlink, MT90401AB Datasheet
MT90401AB
Specifications of MT90401AB
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MT90401AB Summary of contents
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... RSEL RST MS1 MS2 HOLDOVER Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. SONET/SDH System Synchronizer MT90401AB MT90401AB1 Applications • SONET/SDH Add/Drop multiplexers • SONET/SDH uplinks • Integrated access devices • ...
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... SECOOR RST VSS8 VDD5 R Figure 2 - Pin Connections 80 Pin LQFP for MT90401 MT90401 MT90401AB Zarlink Semiconductor Inc. Data Sheet 42 40 FS1 FS2 38 Tdi Trst 36 Tclk Tms 34 Tdo VREF 32 VSS4 C155P 30 C155N VDD 28 VDD2 VSS3 26 IC VSS2 24 PRI SEC 22 E3/DS3 ...
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... C34/C44 pin to output its nominal clock frequency divided Hardware Mode, a high on this pin disables the differential 155.52 MHz output clock on the C155N/C155P pins; this will also cause the C34/C44 pin to output its nominal clock frequency. This pin performs no function if the device is not in Hardware Mode. MT90401 Description 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Internal Connection. Tie low for normal operation. MT90401 Description This is one of two (PRI & SEC) input reference sources This is one of two (PRI & SEC) input reference sources + 16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm. 4 Zarlink Semiconductor Inc. Data Sheet ± 4.6 ppm, the effective out of ...
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... The measurement is done second basis using a signal derived from the 20 MHz clock input on the C20i pin. When the accuracy of the 20 MHz clock is the effective out of range limits of the SECOOR signal will be +7.4 ppm to -16.6 ppm. MT90401 Description 5 Zarlink Semiconductor Inc. Data Sheet ± 4.6 ppm + 16.6 ppm to -7.4 ppm or ...
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... MT90401. When low, the parallel processor is writing data to the MT90401 Address tolerant Input). Address input for the parallel processor interface the least significant input Internal Connection. Tie low for normal operation. MT90401 Description 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Phase Lock Time 4.0 MT90401 and Network Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 TIE Correction (using PCCi 5.3 C155 clock generation and LVDS output drivers 5.4 Microport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5 Output Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MT90401 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 16 - Input to Output Timing for T1/E1 signals (Normal Mode Figure 17 - Input to Output Timing for 19.44 MHz Signal (Normal Mode Figure 18 - Output Timing Figure 19 - Output Timing Figure 20 - Input Controls Setup and Hold Timing Figure 21 - Output Timing MT90401 List of Figures 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 7 - Status Register 1 (Address 01H - Read Only Table 8 - Control Register 2 (Address 04H - Read/Write Table 9 - Set Delay Word 2 (Address 06H - Read/Write Table 10 - Set Delay Word 1 (Address 07H - Read/Write Table 11 - Identification Word (Address 0FH - Read Only MT90401 List of Tables 9 Zarlink Semiconductor Inc. Data Sheet ...
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... The State Machine then returns the device to Normal Mode. MT90401 FS1 Input Frequency 0 0 19.44 MHz See FS2 and FS1 bit description in Table 6 - Control Register 1 (Address 00H - Read/Write kHz 1 0 1.544 MHz 1 1 2.048 MHz Table 1 - Frequency Selection 10 Zarlink Semiconductor Inc. Data Sheet ...
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... The state diagram of Figure 12 indicates the state changes for which the TIE Corrector Circuit is activated. MT90401 TCLR Resets Delay Control Signal Control Circuit Delay Value Compare TIE Corrector Feedback Enable Signal from from Frequency State Machine Select MUX Figure 3 - TIE Corrector Circuit 11 Zarlink Semiconductor Inc. Data Sheet Virtual Reference to DPLL Circuit ...
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... PLL is in Fast Lock Mode. MT90401 Phase Slope Loop Filter Controlled Limiter State Select from Input Impairment Monitor State Select from State Machine Figure 4 - DPLL Block Diagram 12 Zarlink Semiconductor Inc. Data Sheet DPLL Reference Digitally to Output Interface Circuit Oscillator Control Circuit ...
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... C34/C44 pin will output the 8.592 MHz or 11.184 MHz clocks. The 34.368 Mhz and 44.736 MHz clocks have a nominal 50% duty cycle. The duty cycles of the 8.592 MHz and 11.184 MHz signals are dependent on the duty cycle of the 20 MHz clock input to the C20i pin. MT90401 13 Zarlink Semiconductor Inc. Data Sheet ...
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... T1 Divider Tapped Delay Line Tapped Delay 16MHz Line E1 Divider Tapped Delay Line 12MHz DS2 Divider Tapped Delay 19MHz Line C155P PLL Tapped Delay Line C34/C44 8.5/11.2MHz 14 Zarlink Semiconductor Inc. Data Sheet C1.5o C2o C4o C8o C16o F0o F8o F16o C6o C19o ...
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... Select MUX Select Enable Control RSEL State Machine MS1 MS2 RSEL Input Reference 0 PRI 1 SEC Table 2 - Input Reference Selection MS2 MS1 Mode 0 0 NORMAL 0 1 HOLDOVER 1 0 FREERUN 1 1 Reserved Table 3 - Operating Modes and States 15 Zarlink Semiconductor Inc. Data Sheet PCCi ...
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... MT90401 ± 0.02 ppm, which translates to a worst case 14 frame (125 us) slips ± 20 ppm. See Applications - Master Clock section. 16 Zarlink Semiconductor Inc. Data Sheet ± 0.37 ppm (255 frame slips ± 20 ppm output clock is ...
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... Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards (see Figures 7, 8 and 9). MT90401 17 Zarlink Semiconductor Inc. Data Sheet ...
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... For the MT90401, two internal elements determine the jitter attenuation. This includes the low pass loop filter and the phase slope limiter. Both of these parameters have different settings depending on whether the device is in MT90401 18 Zarlink Semiconductor Inc. Data Sheet ...
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... Consequently, a transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example. Example: What is the T1 and E1 output jitter when the T1 input jitter is 20UI (T1 UI Units) and the jitter attenuation is 18 dB? MT90401 19 Zarlink Semiconductor Inc. Data Sheet ...
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... OutputE1 = OutputT1 = ( ) 488ns Normal Freerun (PRI MTIE X / S1H X / S2H Table 4 - Control State Table 20 Zarlink Semiconductor Inc. Data Sheet ( ) ( ) 3.3UI T1 State Normal Holdover Holdover (SEC) (PRI) S2 S1H S1 MTIE S1 S1 MTIE S1 MTIE S1 MTIE S1 MTIE - S2 MTIE S2 MTIE / S2H / S0 S0 (SEC) S2H / - S0 ...
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... S1A>>S1 and S2A>>S2 which may cause frequency step exceeding ±4.6 ppm and longer than 100 sec lock time. Figure 12 - Control State Diagram -9 . This is more accurate than Telcordia’s GR-1244-CORE stratum 3 21 Zarlink Semiconductor Inc. Data Sheet S2 S2A {A} Normal Secondary ...
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... Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a mode change. MT90401 ± 52 ppm minus the accuracy of the master clock ± 20 ppm. TIEmax TIEmin – 22 Zarlink Semiconductor Inc. Data Sheet ...
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... Holdover entered for 2 s with TIE enabled. Each mode change could account for a phase shift as large as 250 ns. Thus, the accumulated phase could be as large as 2.9 us, and, the overall MTIE could be as large as 2.9 us. MT90401 ± 20 ppm, then the capture range will be 23 Zarlink Semiconductor Inc. Data Sheet ± 32 ppm. ...
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... The output pins LOCK, HOLDOVER, SECOOR, PRIOOR function whether the device is in microprocessor mode or hardware mode, but these signals are also available in Status Register 1. The microport provides additional functionality not available in hardware. MT90401 × Phase hold = 0.02ppm 2s = 40ns Phase state = 50ns + 200ns = 250ns × Phase 250ns + 40ns = 24 Zarlink Semiconductor Inc. Data Sheet 2.9us ...
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... Write C16OCNT10,C16OCNT9, C16OCNT8 Read/ C16OCNT7-0 Write Read/ Set all bits to zero. Write Read Only Read Only Read Only Read Only Read Only Table 5 - Register Map 25 Zarlink Semiconductor Inc. Data Sheet Function SECOOR, LOCK, HOLDOVER, E3/DS3, RSV=0, RSV=0, RSV=0, RSV=0, RSV=0, OffEn, ...
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... During the time that FLOCK is one, the wander generation of the PLL is, of necessity, compromised. Set to zero for normal operation. Table 6 - Control Register 1 (Address 00H - Read/Write) MT90401 Read/ Register Write Read Only Read ID7-0 Only Read/ Set all bits to zero. Write Table 5 - Register Map (continued) Functional Description 26 Zarlink Semiconductor Inc. Data Sheet Function ...
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... Functional Description ± 4.6ppm, the effective out of range limits of the + 16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm. ± 4.6 ppm, the effective out of range limits of the + 16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm. Functional Description 27 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 10 - Set Delay Word 1 (Address 07H - Read/Write) Bit Name 7- 0 ID7-0 Identification Word 7-0. These bits contain the revision number of the part. Table 11 - Identification Word (Address 0FH - Read Only) MT90401 Functional Description Functional Description Functional Description 28 Zarlink Semiconductor Inc. Data Sheet ...
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... Min. I DDS 0.7V DD CIH V 0.3V CIL 2 250 1. 300 RF ) unless otherwise stated Zarlink Semiconductor Inc. Data Sheet Min. Max. -0.3 7.0 -0 -55 125 1000 Typ. Max. Units 3.3 3.6 25 +85 ° Max. Units Conditions/Notes 2 mA Outputs unloaded 150 mA Outputs unloaded µA V ...
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... Timing Reference Points Sym. Min. Max DSL t 30 DSH t 0 CSS t 18 RWS t 0 ADS t 0 CSH t 4 RWH t 10 ADH t 50 DDR t 30 DHR t 0 DSW t 10 DHW 30 Zarlink Semiconductor Inc. Data Sheet Sym. CMOS Units IR, OR Units Test Conditions ...
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... TCLR or RST with no further state changes Figure 16 - Input to Output Timing for T1/E1 signals (Normal Mode) MT90401 t DSL t CSS t RWS t t ADS ADH t DDR VALID DATA t t DSW DHW VALID DATA Figure 15 - Microport Timing R15D R2D Zarlink Semiconductor Inc. Data Sheet CSH RWH TT DHR R8D ...
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... R19D t 115 125 F0D F16D t -100 -85 C15D C6D C2D C4D C8D C16D t 315 C15W t 70 C6W t 235 C2W t 115 C4W t 53 C8W t 24 C16W t 9 C19W C155D t 235 250 F0WL t 115 130 F8WH 32 Zarlink Semiconductor Inc. Data Sheet Units Conditions/Notes† ...
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... F16WL 100 S t 100 C34W t 6 C44W t C8.5WL t C11WL t F0WL t F16WL t C8W t t C4W C4W t C2W t C6W t C6W t C15W Figure 18 - Output Timing 1 33 Zarlink Semiconductor Inc. Data Sheet Max. Units Conditions/Notes† 106 F8WH F0D F16D C16D C8D C4D C2D ...
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... C19W C19o t C155D C155p C155n F8o MS1,2, RSEL, PCCi Figure 20 - Input Controls Setup and Hold Timing C34o t C44W C44o t C 8.5 C8.5o t C11 C11o MT90401 t C19W t C155D Figure 19 - Output Timing Figure 21 - Output Timing 3 34 Zarlink Semiconductor Inc. Data Sheet LVH V LVL ...
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... MAX UIpp MAX ns-pp 0.004 2.76 0.004 1.83 0.100 5.20 0.100 5.16 0.044 1.30 0.039 1.15 0.044 0.99 0.037 0.82 35 Zarlink Semiconductor Inc. Data Sheet Units Conditions/Notes† Units Conditions/Notes† ppm ppm ppm ppm 4.6 ppm frequency s offset us per 1 ...
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... NA 4.7 NA 4.0 NA 3.1 36 Zarlink Semiconductor Inc. Data Sheet Notes Filter: 100 Hz - 400 kHz OC-1 Filter: 20 kHz - 400 kHz OC-1 Filter: 500 Hz - 1.3 MHz OC-3 Filter: 65 kHz - 1.3 MHz OC-3 Notes ...
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