MT90401AB Zarlink, MT90401AB Datasheet - Page 26

• Manufacturer Part Number: MT90401AB
• Description: Framer SDH/SONET 3.3V 80-Pin LQFP EP Tray
• Manufacturer: Zarlink

Specifications of MT90401AB

• Package: 80LQFP EP
• Number Of Transceivers: 1
• Standard Framing Format: SDH|SONET
• Maximum Supply Current: 150 mA
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V

6 - 5
4 - 3
Control and Status Registers (continued)
0EH
0FH (Table 11)
10H
Bit
(A
7
2
1
6
A
5
Address
SONET/SDH
A
4
A
FLOCK
MS2-1
Name
FS2-1
RSEL
3
A
2
A
1
A
0
)
Reserved
Identification Word
Reserved
Reference Select. A zero selects the PRI (primary) reference source as the input
reference signal and a one selects the SEC (secondary) reference. Switching between
reference clocks operating at 8 kHz, 1.544 MHz and 2.048 MHz can be done at any time
and without any special setup procedures. However it is recommended that the switching
of the 19.44 MHz references will be performed by forcing PLL temporary into Holdover
mode (MS2,MS1=01) to prevent excessive phase accumulation in the internal controller.
The PLL can be switched back to Normal mode (MS2,MS1= 00) 250 us after the new
input reference has been selected.
Frequency Select 2 - 1. These bits select which of four possible frequencies (8 kHz,
1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI and SEC inputs.
FS2 - 0, FS1 - 0 = 19.44 MHz
FS2 - 0, FS1 - 1 = 8 kHz.
FS2 - 1, FS1 - 0 = 1.544 MHz.
FS2 - 1, FS1 - 1 = 2.048 MHz.
When “19.44 MHz” reference clock option is selected, a loss of 19.44 MHz clock or a
larger than 30000 ppm frequency deviation may create a frequency step exceeding ±4.6
ppm upon return from Auto-Holdover mode. This may result in a lock time that is longer
than normally guaranteed.
Mode Select 2 - 1: These bits select the PLL state of operation.
MS2 - 0, MS1 - 0 = Normal.
MS2 - 0, MS1 - 1 = Holdover.
MS2 - 1, MS1 - 0 = Freerun.
MS2 - 1, MS1 - 1 = Reserved.
SONET / SDH. Set to one to move the loop filter corner frequency to 70 millihertz and
limit the phase slope to 885 ns per second as per SONET requirements. Set to zero to
move the corner frequency to 1.1 Hz and limit the phase slope to 53 ns per 1.326 ms.
Fast Lock. Set to one to allow the PLL to lock faster than normal to the input reference.
During the time that FLOCK is one, the wander generation of the PLL is, of necessity,
compromised. Set to zero for normal operation.
Table 6 - Control Register 1 (Address 00H - Read/Write)
Register
Table 5 - Register Map (continued)
Zarlink Semiconductor Inc.
MT90401
26
Functional Description
Read/
Read/
Write
Read
Read
Write
Only
Only
ID7-0
Set all bits to zero.
Function
Data Sheet