MT90401AB1 Zarlink, MT90401AB1 Datasheet - Page 12

• Manufacturer Part Number: MT90401AB1
• Description: Framer SDH/SONET 3.3V 80-Pin LQFP EP Tray
• Manufacturer: Zarlink

Specifications of MT90401AB1

• Package: 80LQFP EP
• Number Of Transceivers: 1
• Standard Framing Format: SDH|SONET
• Maximum Supply Current: 150 mA
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V

MT90401
Data Sheet
1.4
Digital Phase Lock Loop (DPLL)
As shown in Figure 4, the DPLL of the MT90401 consists of a Phase Detector, Phase Slope Limiter, Loop Filter,
Digitally Controlled Oscillator, and a Control Circuit.
Virtual Reference
DPLL Reference
Digitally
Phase
Phase Slope
from
to
Loop Filter
Controlled
Detector
Limiter
TIE Corrector
Output Interface Circuit
Oscillator
Feedback Signal
State Select
Control
from
from
Circuit
Frequency Select MUX
Input Impairment Monitor
State Select
from
State Machine
Figure 4 - DPLL Block Diagram
Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the
feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase
difference between the two. This error signal is passed to the Phase Slope Limiter circuit. The Frequency Select
MUX allows the proper feedback signal to be externally selected (e.g., 8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz).
Phase Slope Limiter - the Phase Slope Limiter receives the error signal from the Phase Detector and ensures that
the DPLL responds to all input transient conditions with a limited output phase slope. In SONET Mode the
maximum output phase slope is limited to 885 ns/s as per Telcordia GR-253-CORE. In SDH Mode the maximum
output phase slope is 53 ns per 1.326 ms.
Loop Filter - the Loop Filter is a low pass filter, that defines the network jitter and wander transfer requirements for
all input reference frequencies (8 kHz, 1.544 MHz, 2.048 MHz, or 19.44 MHz). In SONET mode the loop filter has a
cut-off frequency of 70 mHz to comply with Telcordia GR-253-CORE and GR-1244-CORE. In SDH mode the loop
filter has a cut-off frequency of 1.1Hz to comply with ITU-T G.813 Option 1 and GR-1244-CORE.
Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input
Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the MT90401.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover Mode, the DCO is free running at a frequency equal to the last locked frequency the DCO was
generating while in Normal Mode. In order to improve accuracy of the Holdover Mode the actual frequency sample
is taken 30 to 60 ms before switching into holdover.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the C20i 20 MHz source.
Telcordia GR-253-CORE requires that, during recovery from holdover, SONET clocks not change their output
frequency at a rate faster than 2.9 ppm per second. In SONET Mode the MT90401 limits the rate of change of its
output frequency (frequency slope) to less than 1.9ppm per second; this limit remains in place when the PLL is in
Fast Lock Mode.
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Zarlink Semiconductor Inc.