723631L15PF Integrated Device Technology (Idt), 723631L15PF Datasheet - Page 14

• Manufacturer Part Number: 723631L15PF
• Description: FIFO Mem Sync Dual Depth Bi-Dir 512 x 36 120-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723631L15PF

• Package: 120TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 18 Kb
• Organization: 512x36
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Expansion Type: Depth
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTE:
1. It is not necessary to program Offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH.
FS1/SEN
A0 - A35
B0 - B35
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
FS0/SD
CLKB
W/RB
W/RA
CLKA
MBB
CLKA
MBA
ENB
ENA
CSB
CSA
OR
RST
IR
IR
HIGH
HIGH
t
t
CLKH
CLKH
t
t
FSS
FSS
Figure 4. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values Serially
4
t
EN
t
t
CLK
CLK
t
t
t
ENS2
t
t
MDV
ENS2
ENS1
ENS2
t
t
DS
FSH
t
t
CLKL
CLKL
t
t
SPH
ENS1
W1
W1
t
SENS
t
t
t
t
t
t
t
SDS
t
ENH2
Figure 5. FIFO Write Cycle Timing
Figure 6. FIFO Read Cycle Timing
ENH2
ENH1
DH
ENH1
A
ENH2
AF Offset
(Y) MSB
t
t
SENH
SDH
t
ENS1
14
W2
t
ENS1
W2
t
t
t
A
ENH1
ENH1
t
SENS
t
SDS
AE Offset
(X) LSB
No Operation
t
ENS1
No Operation
t
COMMERCIAL AND INDUSTRIAL
t
t
ENS1
SENH
SDH
W3
TEMPERATURE RANGES
t
ENH1
t
ENH1
t
PIR
t
DIS
3023 drw08
3023 drw09
3023 drw07