ADF7023-JBCPZ-RL Analog Devices Inc, ADF7023-JBCPZ-RL Datasheet
ADF7023-JBCPZ-RL
Specifications of ADF7023-JBCPZ-RL
Related parts for ADF7023-JBCPZ-RL
ADF7023-JBCPZ-RL Summary of contents
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... LNA RFIO_1P RSSI/ LOGAMP RFIO_1N PA LOOP DIVIDER PA RFO2 FILTER PA RAMP PROFILE ADF7023-J CREGRFx CREGVCO CREGSYNTH CREGDIGx 1 GPIO REFERS TO PINS 17, 18, 19, 20, 25, AND 27. ADCIN_ATB3 FSK ASK DEMOD 8-BIT RISC 8-BIT PROCESSOR ADC CDR AFC AGC 26MHz OSC CHARGE PFD PUMP DIVIDER f DEV GAUSSIAN Σ ...
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SCLK MISO BIT 7 BIT 6 BIT MOSI SCLK MISO SPI STATE SLEEP WAKE ...
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... CREGRF1 MOSI RBIAS ADF7023-J CREGRF2 3 22 SCLK RFIO_1P 4 21 MISO TOP VIEW 5 20 IRQ_GP3 RFIO_1N (Not to Scale GP2 RFO2 7 EPAD 18 GP1 VDDBAT2 GP0 NOTES CONNECT. DO NOT CONNECT TO THIS PIN. 2. CONNECT EXPOSED PAD TO GND. ...
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PA SETTING 36 34 –40°C, ...
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PA RAMP = 4 –30 PA RAMP = 5 PA RAMP = 6 –40 PA RAMP = 7 –50 – ...
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IIP3 = –12.2dBm –40 –50 –60 FUNDAMENTAL TONE –70 IM3 TONE FUNDAMENTAL 1/1 SLOPE FIT –80 IM3 3/1 SLOPE FIT –90 –50 –45 –40 –35 –30 –25 –20 LNA INPUT POWER (dBm ...
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Blocker frequency offset (MHz -10 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 Blocker ...
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CALIBRATED UNCALIBRATED –10 –20 –30 –40 –50 –60 –70 –80 –90 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz) 0 100kHz BW 150kHz BW –10 200kHz BW 300kHz BW –20 –30 –40 ...
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Coded,PML=0x0A,Sync. Tol.=0 9 Coded,PML=0x0A,Sync. Tol.=1 8 Coded,PML=0x07,Sync. Tol.=2 7 Uncoded,PML=0x0A,Sync.Tol.= 2.1dB 3 3.5dB 2 4.1dB 1 0 -109 -108 -107 -106 -105 -104 -103 Rx Input Power (dBm) 0 100kbps 150kbps –10 200kbps –20 300kbps –30 ...
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INPUT POWER (dBm) –20 IDEAL RSSI MEAN RSSI –30 MEAN RSSI (WITH POLYNOMIAL CORRECTION) –40 –50 –60 –70 –80 –90 –100 MEAN RSSI ERROR –110 ...
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COLD START (BATTERY APPLIED) CMD_CONFIG_DEV CONFIGURE CMD_RAM_LOAD_INIT PROGRAM RAM CMD_RAM_LOAD_DONE CONFIG 2 PROGRAM RAM AES IR CALIBRATION REED-SOLOMON TX_EOF CMD_PHY_TX 1 TRANSMIT AND RECEIVE AUTOMATIC TURNAROUND MUST BE ENABLED BY BITS RX_TO_TX_AUTO_TURNAROUND AND TX_TO_RX_AUTO_TURNAROUND (0x11A: MODE_CONTROL). 2 AES ENCRYPTION/DECRYPTION, IMAGE ...
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• • • • ...
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SYNC PREAMBLE PAYLOAD WORD ...
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PHY_TX CMD_PHY_TX PA 300µs RAMP PACKET PREAMBLE GP2 (TX CLK) GP1 (TX DATA) IRQ_GP3 (CMD_FINISHED INTERRUPT) GP2 (TX CLK) GP1 (TX DATA) PHY_RX CMD_PHY_RX 309µs PACKET PREAMBLE GP2 (RX CLK) GP0 (RX DATA) GP4 GP2 (RX CLK) GP0 (RX DATA) ...
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PHY_RX CMD_PHY_RX 309µs PACKET PREAMBLE GP2 (RX CLK) GP0 (RX DATA) GP4 (GPIO_CONFIGURE = 0xA1) GP4 (GPIO_CONFIGURE = 0xA2) PREAMBLE DETECTED GP2 (RX CLK) GP0 (RX DATA) GP4 (GPIO_CONFIGURE = 0xA1) GP4 (GPIO_CONFIGURE = 0xA2) PHY_RX CMD_PHY_RX 309µs PACKET PREAMBLE ...
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FIRST BIT SENT MSB 24 BITS ≥ SYNC_WORD_LENGTH > 16 BITS SYNC_BYTE_0 APPEND UNUSED BITS WITH PREAMBLE (0101..) MSB 16 BITS ≥ SYNC_WORD_LENGTH > 8 BITS SYNC_BYTE_1 APPEND UNUSED BITS WITH PREAMBLE (0101..) MSB SYNC_WORD_LENGTH ≤ 8 BITS SYNC_BYTE_2 APPEND ...
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TX PAYLOAD LENGTH = PACKET_LENGTH_MAX RX PAYLOAD LENGTH = PACKET_LENGTH_MAX SYNC PAYLOAD FIXED PREAMBLE WORD TX PAYLOAD LENGTH = LENGTH RX PAYLOAD LENGTH = LENGTH + LENGTH_OFFSET – 4 SYNC VARIABLE PREAMBLE LENGTH WORD CRC PAYLOAD CRC ...
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ADDRESS_MATCH_OFFSET SYNC ADDRESS PREAMBLE WORD DATA PAYLOAD CRC ...
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CMD_PHY_TX PA OUTPUT TX DATA COMMUNICATIONS PROCESSOR FW_STATE RAMP TIME ~19µs PREAMBLE 300µs 142µs 55µs PA VCO CAL SYNTH RAMP = 0x00 (BUSY) 1 BYTE RAMP TIME SYNC PAYLOAD CRC POSTAMBLE WORD PA PHY_TX RAMP = 0x14 (PHY_TX) ...
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ADDRESS CS MISO SPI MOSI SCLK SPI/CP MEMORY ARBITRATION COMMS PROCESSOR COMMS PROCESSOR 8-BIT ADDRESS/ CLOCK RISC DATA ENGINE MUX 11-BIT ADDRESSES 0x3FF PROGRAM MCR RAM 256 BYTES [12:0] 2kB 0x300 NOT USED PROGRAM ROM 0x13F 4kB BBRAM 64 BYTES ...
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TRANSMIT AND RECEIVE PACKET TX_BASE_ADR 0x010 TRANSMIT PAYLOAD RX_BASE_ADR RECEIVE PAYLOAD 0x0FF 240 BYTE TRANSMIT OR RECEIVE PACKET TX_BASE_ADR 0x010 RX_BASE_ADR TRANSMIT OR RECEIVE PAYLOAD 0x0FF MULTIPLE TRANSMIT AND RECEIVE PACKETS TX_BASE_ADR 0x010 (PACKET 1) TRANSMIT PAYLOAD TX_BASE_ADR (PACKET 2) ...
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... GPIO CS SCLK SCLK ADF7023-J MOSI MOSI MISO MISO IRQ IRQ_GP3 CS MOSI MISO HOST PROCESSOR CS MOSI MISO CMD IGNORE SPI_NOP SPI_NOP IGNORE STATUS ...
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CMD_PHY_ON CS CMD_READY FW_STATE = 0x11 (PHY_OFF) 0xB1 STATUS WORD COMMUNICATIONS WAITING FOR COMMAND PROCESSOR ACTION CMD_PHY_ON CS CMD_READY FW_STATE = 0x11 (PHY_OFF) STATUS WORD 0xB1 COMMUNICATIONS WAITING FOR COMMAND PROCESSOR ACTION ISSUE = 0x00 (BUSY) 0xA0 0x80 TRANSITION RADIO ...
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CS SPI MEMORY ACCESS COMMAND MOSI 5 BITS • • • • • MEMORY ADDRESS BITS[7:0] MEMORY ADDRESS BITS[10:0] DATA BYTE DATA n × 8 BITS ...
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CS SPI_MEM_WR ADDRESS MOSI IGNORE STATUS MISO CS SPI_MEMR_WR ADDRESS 1 MOSI IGNORE STATUS MISO • • • • • • DATA FOR DATA FOR DATA FOR [ADDRESS] [ADDRESS + 1] [ADDRESS + 2] STATUS STATUS STATUS DATA FOR DATA ...
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CS SPI_MEM_RD MOSI IGNORE MISO CS SPI_MEMR_RD ADDRESS 1 MOSI MISO IGNORE STATUS ADDRESS SPI_NOP SPI_NOP DATA FROM STATUS STATUS ADDRESS ADDRESS 2 ADDRESS 3 ADDRESS 4 DATA FROM DATA FROM STATUS ADDRESS 1 ADDRESS 2 MAX N = (256-INITIAL ...
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... ADF7023-J PHY_SLEEP BBRAM RETAINED? WUC CONFIGURED? INCREMENT NUMBER_OF_WAKEUPS NUMBER_OF_WAKEUPS > THRESHOLD? SWM ENABLED? NO (SWM_EN = 1) YES RSSI QUAL ENABLED? MEASURE RSSI (SWM_RSSI_QUAL) NO RSSI > THRESHOLD (SWM_RSSI_THRESH) YES RSSI INT ENABLED? YES (INTERRUPT_ SWM_RSSI_DET) NO PREAMBLE DETECTED? NO AND RX_DWELL_TIME EXCEEDED SYNC WORD DETECTED CORRECT? NO ADDRESS MATCH? ...
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... PHY_ON OPERATION INTERRUPT_ NUM_WAKEUPS HOST: CMD_PHY_SLEEP HOST: START WUC PHY_OFF OR ADF7023-J PHY_ON OPERATION WUC TIMEOUT PERIOD INTERRUPT_ SWM_RSSI_DET HOST: CMD_PHY_SLEEP HOST: START WUC ADF7023-J PHY_OFF OR PHY_ON OPERATION WUC TIMEOUT PERIOD INTERRUPT_ SWM_RSSI_DET INTERRUPT_ PREAMBLE_DETECT INTERRUPT_ SYNC_DETECT INTERRUPT_ CRC_CORRECT INTERRUPT_ ADDRESS_MATCH HOST: CMD_PHY_SLEEP ...
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... WUC WUC_CONFIG_LOW[ OSCILLATOR 32.768kHz 32kHz XTAL 0 WUC_VALUE_HIGH 16-BIT WUC_CONFIG_HIGH[2:0] RELOAD VALUE TICK RATE 16-BIT DOWN PRESCALER COUNTER WUC_VALUE_LOW ADF7023-J WAKE-UP CIRCUIT WUC_TIMEOUT INTERRUPT TO FIRMWARE TIMER + ...
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BYTES SYNC PREAMBLE PAYLOAD WORD k BYTES ECC (n – k) BYTES ...
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PLAIN TEXT 128 BITS KEY AES ENCRYPT 128 BITS CYPHER TEXT PLAIN TEXT 128 BITS + INITIAL VECTOR KEY KEY AES ENCRYPT 128 BITS CYPHER TEXT ECB MODE 128 BITS 128 BITS KEY KEY AES AES ENCRYPT ENCRYPT 128 BITS ...
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CALIBRATION 26MHz CHARGE REF PFD PUMP LOOP FILTER N DIVIDER TX FRAC-N DATA Σ-∆ DIVIDER GAUSSIAN FILTER INTEGER-N F_DEVIATION • • VCO RF FREQ ÷2 VCO ÷2 ...
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DATA BITS PA RAMP 1 (256 CODES PER BIT) PA RAMP 2 (128 CODES PER BIT) PA RAMP 3 (64 CODES PER BIT) PA RAMP 4 (32 CODES PER BIT) PA RAMP 5 (16 CODES ...
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IF FILTER MIXER LNA RFIO_1P RFIO_1N IF IFBW[1:0] (ADDRESS RADIO_CFG_9[7:6]) AFC SYSTEM RF RANGE SYNTHESIZER (LO) MAX_AFC_RANGE[7:0] × = FREQUENCY POST-DEMOD LIMITERS CORRELATOR FILTER I Q POST_DEMOD_BW[7:0] DISCRIM_PHASE[1:0] DISCRIM_BW[7: AVERAGING PI FILTER CONTROL AFC_LOCK_MODE[1:0] AFC_KI[3:0] (ADDRESS RADIO_CFG_11[7:4]) AFC_KP[3:0] ...
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... CS 23 MOSI 22 SCLK 21 MISO 20 IRQ_GP3 19 GP2 18 GP1 17 GP0 32kHz XTAL (OPTIONAL) 1 CREGRF1 2 RBIAS 3 CREGRF2 4 RFIO_1P 5 IRQ_GP3 RFIO_1N ADF7023-J 6 RFO2 GND PAD 7 VDD VDDBAT2 8 NC 26MHz XTAL V DD GPIO MOSI SCLK MISO IRQ DD IRQ GPIO MOSI SCLK MISO IRQ TxRxCLK TxDATA RxDATA ...
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... MATCH HARMONIC ANTENNA FILTER CONNECTION HARMONIC ANTENNA FILTER CONNECTION LNA MATCH RX HARMONIC FILTER TX PA MATCH ADF7023-J 3 CREGRF2 4 RFIO_1P 5 RFIO_1N 6 RFO2 ADF7023-J 3 CREGRF2 4 RFIO_1P 5 RFIO_1N 6 RFO2 ADF7023-J 3 CREGRF2 4 RFIO_1P 5 RFIO_1N 6 RFO2 ...
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... DIFFERENTIAL PA AND LNA MATCH TX (DIFFERENTIAL HARMONIC PA) AND RX FILTER TX (SINGLE- HARMONIC ENDED PA) FILTER ADF7023-J 3 CREGRF2 4 RFIO_1P 5 RFIO_1N 6 RFO2 SINGLE-ENDED PA MATCH ...
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SQ 4.90 PIN 1 INDICATOR TOP VIEW 0.80 0.75 0.70 SEATING 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 0.30 0.25 0. 0.50 BSC 3.45 EXPOSED PAD 3. ...
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