ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet
ADF7023-JBCPZ
Specifications of ADF7023-JBCPZ
Related parts for ADF7023-JBCPZ
ADF7023-JBCPZ Summary of contents
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... LFCSP package APPLICATIONS Smart metering IEEE 802.15.4g Home automation Process and building control Wireless sensor networks (WSNs) Wireless healthcare One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ADF7023-J www.analog.com ©2011 Analog Devices, Inc. All rights reserved. ...
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... Sync Word ................................................................................... 39 Payload......................................................................................... 40 CRC .............................................................................................. 41 Postamble..................................................................................... 42 Transmit Packet Timing ............................................................ 42 Data Whitening .......................................................................... 43 Manchester Encoding ................................................................ 43 8b/10b Encoding ........................................................................ 43 Interrupt Generation...................................................................... 44 Interrupts in Sport Mode .......................................................... 46 ADF7023-J Memory Map ............................................................. 47 BBRAM........................................................................................ 47 Modem Configuration RAM (MCR) ...................................... 47 Program ROM ............................................................................ 47 Program RAM ............................................................................ 47 Packet RAM ................................................................................ 48 ...
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... REVISION HISTORY 5/11—Revision 0: Initial Version Register Maps ..................................................................................78 BBRAM Register Description ...................................................80 MCR Register Description.........................................................90 Packet RAM Register Description............................................97 Outline Dimensions........................................................................98 Ordering Guide ...........................................................................98 Rev Page 3 of 100 ADF7023-J ...
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... Figure 1. calibration can be stored in nonvolatile memory for use on subsequent power-ups of the transceiver. The ADF7023-J operates with a power supply range of 2 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance. The device can enter a low power sleep mode in which the configuration settings are retained in the battery backup random access memory (BBRAM) ...
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... CRC and store the received payload to packet RAM. The ADF7023-J uses an efficient interrupt system comprising MAC level interrupts and PHY level interrupts that can be individually set. The payload data plus the 16-bit CRC can be encoded/decoded using Manchester or 8b/10b encoding ...
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... ADF7023-J SPECIFICATIONS V = VDDBAT1 = VDDBAT2 = 2 3.6 V, GND = and T = 25° AND SYNTHESIZER SPECIFICATIONS Table 1. Parameter RF CHARACTERISTICS Frequency Range PHASE-LOCKED LOOP Channel Frequency Resolution Phase Noise at Offset of 600 kHz 800 kHz 600 kHz 800 kHz 1 MHz 2 MHz 10 MHz VCO Calibration Time Synthesizer Settling Time ...
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... Rev Page 7 of 100 ADF7023-J Test Conditions/Comments RF frequency = 957.2 MHz, GFSK Modulation index = 1 Modulation index = 1 Modulation index = 0.5 Modulation index = 0.5 Modulation index = 0.5 2 With T96 look-up table (LUT) Modulation index = 1 Modulation index = 1 Modulation index = 1 Modulation index = 0 ...
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... ADF7023-J Parameter SPURIOUS EMISSIONS 30 MHz to 710 MHz 710 MHz to 945 MHz 945 MHz to 950 MHz 958 MHz to 960 MHz 960 MHz to 1 GHz 1 GHz to 1.215 GHz 1.215 GHz to 1.8845 GHz 5 1.8845 GHz to 1.9196 GHz 1.9196 GHz to 3 GHz 3 GHz to 5 GHz ...
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... Frequency deviation = 25 kHz, IF filter bandwidth = 100 kHz −101 dBm Frequency deviation = 37.5 kHz, IF filter bandwidth = 150 kHz −99.1 dBm Frequency deviation = 50 kHz, IF filter bandwidth = 200 kHz −97.9 dBm Frequency deviation = 75 kHz, IF filter bandwidth = 300 kHz Rev Page 9 of 100 ADF7023 ...
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... ADF7023-J Parameter GFSK/GMSK INPUT SENSITIVITY, PER 50 kbps 100 kbps 100 kbps 200 kbps 200 kbps LNA AND MIXER, INPUT IP3 Minimum LNA Gain Maximum LNA Gain LNA AND MIXER, INPUT IP2 Maximum LNA Gain, Maximum Mixer Gain Minimum LNA Gain, Minimum Mixer Gain ...
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... Bits Sync word tolerance = 1 −97 to −26 dBm ±2 dB ± dBm 75.9 − Ω j32.3 74.6 − Ω j32.5 7.7 + j8.6 Ω 7.7 + j8.9 Ω −66 dBm At antenna input, unfiltered conductive −62 dBm At antenna input, unfiltered conductive Rev Page 11 of 100 ADF7023-J ...
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... V 0 Rev Page 12 of 100 ADF7023-J-J Test Conditions/Comments See the State Transition and Command Timing section for more details Includes VCO calibration and synthesizer settling Includes VCO calibration and synthesizer settling, does not include PA ramp- 500 μ 500 μA OL ...
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... Rev Page 13 of 100 ADF7023-J Test Conditions/Comments After calibration After calibration at 25°C 32.768 kHz crystal with 7 pF load capacitance Firmware counter counts of the number of hardware wake-ups, resolution of 16 bits From 2 3 25°C A From 2 ...
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... ADF7023-J GENERAL SPECIFICATIONS Table 6. Parameter TEMPERATURE RANGE VOLTAGE SUPPLY V DD TRANSMIT CURRENT CONSUMPTION Single-Ended PA, 915 MHz −10 dBm 0 dBm 10 dBm 13.5 dBm Differential PA, 915 MHz −10 dBm 0 dBm 5 dBm 10 dBm POWER MODES PHY_SLEEP (Deep Sleep Mode 2) PHY_SLEEP (Deep Sleep Mode 1) PHY_SLEEP (RCO Wake Mode) ...
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... CS low to MISO high wake-up time, SCLK rise time SCLK fall time BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT Figure 2. SPI Interface Timing WAKE UP Rev Page 15 of 100 , unless otherwise noted. MAX 26 MHz crystal with 7 pF load capacitance BIT 7 BIT SPI READY ADF7023-J = 25°C A BIT 7 7 ...
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... ADF7023-J ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Connect the exposed paddle A of the LFCSP package to ground. Table 8. Parameter VDDBAT1, VDDBAT2 to GND Operating Temperature Range Industrial Storage Temperature Range Maximum Junction Temperature LFCSP θ Thermal Impedance JA Reflow Soldering Peak Temperature ...
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... RBIAS 2 23 MOSI ADF7023-J CREGRF2 3 22 SCLK RFIO_1P 4 21 MISO TOP VIEW RFIO_1N 5 20 IRQ_GP3 (Not to Scale GP2 RFO2 7 EPAD 18 GP1 VDDBAT2 GP0 NOTES CONNECT. DO NOT CONNECT TO THIS PIN. 2. CONNECT EXPOSED PAD TO GND. Figure 4. Pin Configuration Rev Page 17 of 100 ADF7023-J ...
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... MOSI Serial Port Master Out/Slave In Chip Select (Active Low). A pull-up resistor of 100 kΩ processor from inadvertently waking the ADF7023-J from sleep. 25 GP4 Digital GPIO Test Pin 4. 26 CREGDIG2 Regulator Voltage for Digital Section of the Chip. A 220 nF capacitor should be placed between this pin and ground for regulator stability and noise rejection ...
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... Each PA_RAMP Setting, Differential RAMP = 1 PA RAMP = 2 PA RAMP = 3 PA RAMP = 4 PA RAMP = 5 PA RAMP = 6 PA RAMP = 100 150 200 250 300 350 400 TIME (µs) Figure 10. PA Ramp-Down at Data Rate = 38.4 kbps for Each PA_RAMP Setting, Differential PA ADF7023-J 450 500 450 500 ...
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... ADF7023 –10 –20 PA RAMP = 4 –30 PA RAMP = 5 PA RAMP = 6 –40 PA RAMP = 7 –50 – TIME (µs) Figure 11. PA Ramp-Up at Data Rate = 300 kbps for Each PA_RAMP Setting, Differential –10 –20 PA RAMP = 4 –30 PA RAMP = 5 PA RAMP = 6 –40 PA RAMP = 7 –50 – TIME (µs) Figure 12. PA Ramp-Down at Data Rate = 300 kbps for ...
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... Rev Page 21 of 100 MODULATED INTERFERER 40 CARRIER WAVE INTERFERER –10 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz MODULATED 40 INTERFERER CARRIER WAVE 30 INTERFERER –10 –20 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz MODULATED INTERFERER 30 CARRIER WAVE INTERFERER –10 –20 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz) ADF7023-J ...
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... ADF7023 25°C, 3.0V –10 –60 –50 –40 –30 –20 – BLOCKER FREQUENCY OFFSET (MHz) Figure 23. Receiver Wideband Blocking at 954 MHz, Data Rate = 50 kbps, Frequency Deviation = 25 kHz, Carrier Wave Interferer –10 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 BLOCKER FREQUENCY OFFSET (MHz) Figure 24. Receiver Close-In Blocking at 954 MHz, Data Rate = 50 kbps, ...
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... APPLIED RECEIVER POWER (dBm) = 3.0 V, Temperature = 25°C DD +25°C +85°C –40°C 1.8 3.6 V (V) DD Deviation = 75 kHz, IF Bandwidth = 300 kHz ADF7023-J 250 300 = 3 1kbps 10kbps 38.4kbps 50kbps 100kbps 200kbps 300kbps –10 0 ...
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... ADF7023 2.1dB 3 3.5dB 2 4.1dB 1 0 –107 –106 –105 –104 –103 –102 Rx INPUT POWER (dBm) Figure 35. Receiver PER Using Reed Solomon (RS) Coding; RF Frequency = 928 MHz, GFSK, Data Rate = 100 kbps, Frequency Deviation = 50 kHz, Packet Length = 28 Bytes (Uncoded); Reed Solomon Configuration 38 28 PML = Preamble Match Level Register ...
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... IFBW = 200kHz DISC BW (kHz) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 MODULATION INDEX = ±(MI × 50 kHz), Data = PRBS9, BER = 1E − 3, DEV Bits = 3.0 V, Temperature = 25°C BAT ADF7023 220 210 200 190 180 170 160 150 140 130 120 110 100 ...
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... ADF7023-J TERMINOLOGY ADC Analog-to-digital converter AGC Automatic gain control AFC Automatic frequency control Battmon Battery monitor BBRAM Battery backup random access memory CBC Cipher block chaining CRC Cyclic redundancy check DR Data rate ECB Electronic code book ECC Error checking code 2FSK ...
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... RADIO CONTROL The ADF7023-J has five radio states designated PHY_SLEEP, PHY_OFF, PHY_ON, PHY_TX, and PHY_RX. The host processor can transition the ADF7023-J between states by issuing single byte commands over the SPI interface. The various commands and states are illustrated in Figure 47. The communications ...
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... ADF7023-J COLD START (BATTERY APPLIED) CMD_CONFIG_DEV CONFIGURE CMD_RAM_LOAD_INIT PROGRAM RAM CMD_RAM_LOAD_DONE CONFIG 2 PROGRAM RAM AES IR CALIBRATION REED-SOLOMON 1 TRANSMIT AND RECEIVE AUTOMATIC TURNAROUND MUST BE ENABLED BY BITS RX_TO_TX_AUTO_TURNAROUND AND TX_TO_RX_AUTO_TURNAROUND (0x11A: MODE_CONTROL). 2 AES ENCRYPTION/DECRYPTION, IMAGE REJECTION CALIBRATION, AND REED SOLOMON CODING ARE AVAILABLE ONLY IF THE NECESSARY FIRMWARE MODULE HAS BEEN DOWNLOADED TO THE PROGRAM RAM ...
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... Wait for the CMD_READY bit in the status word to go high. 4. Issue the CMD_CONFIG_DEV command so that the radio settings are updated using the BBRAM values. The ADF7023-J is now configured and ready to transition to the PHY_ON state. Initialization After a WUC Timeout The ADF7023-J can autonomously wake from the PHY_SLEEP state using the wake-up controller ...
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... RSSI, IF filter, mixer, and LNA). 5. Sets FW_STATE = PHY_ON. CMD_PHY_SLEEP (0xBA) This command transitions the ADF7023-J to the very low power PHY_SLEEP state in which the WUC is operational (if enabled), and the BBRAM contents are retained. It can be issued from the PHY_OFF or PHY_ON state. CMD_PHY_RX (0xB2) This command can be issued in the PHY_ON, PHY_RX, or PHY_TX state ...
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... PHY_OFF or PHY_ON state. CMD_GET_RSSI (0xBC) This command turns on the receiver, performs an RSSI measure- ment on the current channel, and returns the ADF7023-J to the PHY_ON state. The command can be issued from the PHY_ON state. The RSSI result is saved to the RSSI_READBACK register (Address 0x312) ...
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... In sport mode, the TX_TO_RX_AUTO_TURNAROUND transition is disabled. WUC Timeout The ADF7023-J can use the WUC to wake from sleep on a timeout of the hardware timer. The device wakes into the PHY_OFF state. See the WUC Mode section for further details. Rev Page 32 of 100 ...
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... The execution times for all radio state transitions are detailed in Table 11 and Table 12. Note that these times are typical and can vary, depending on the BBRAM configuration. Table 11. ADF7023-J Command Execution Times and State Transition Times That Are Not Related to PHY_TX or PHY_RX Command ...
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... ADF7023-J Command/Bit/ Automatic Present Mode Transition State Packet CMD_PHY_RX PHY_RX Packet TX_TO_RX_AUTO_ PHY_TX TURNAROUND Packet TX_EOF PHY_TX Packet RX_EOF PHY_RX Sport CMD_PHY_ON PHY_TX Sport CMD_PHY_ON PHY_RX Sport CMD_PHY_TX PHY_ON Sport CMD_PHY_TX PHY_RX Sport CMD_PHY_TX PHY_TX Sport PHY_RX RX_TO_TX_AUTO _TURNAROUND Sport CMD_PHY_RX ...
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... SPORT MODE It is possible to bypass all of the packet management features of the ADF7023-J and use the sport interface for transmit and receive data. The sport interface is a high speed synchronous serial interface allowing direct interfacing to processors and DSPs. Sport mode is enabled using the DATA_MODE setting in the PACKET_LENGTH_CONTROL register (Address 0x126), as described in Table 13 ...
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... ADF7023-J Table 14. GPIO Functionality in Sport Mode GPIO_CONFIGURE GP0 GP1 0xA0 Rx data Tx data 0xA1 Rx data Tx data 0xA2 Rx data Tx data 0xA3 Rx data Tx data 0xA4 Rx data Tx data 0xA5 Rx data Tx data 0xA6 Rx data Tx data 0xA7 Rx data Tx data 0xA8 Rx data Tx data CMD_PHY_TX 300µs PACKET GP2 (TX CLK) ...
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... GP0 (RX DATA) GP4 (GPIO_CONFIGURE = 0xA1) GP4 (GPIO_CONFIGURE = 0xA2) Figure 52. Sport Mode Receive, DATA_MODE = 2, GPIO_CONFIGURE = 0xA1, 0xA2, 0xA4, 0xA5, 0xA7, 0xA8 SYNC PAYLOAD WORD 8/(DATA RATE) SYNC PAYLOAD WORD Rev Page 37 of 100 ADF7023-J PHY_ON CMD_PHY_ON 55.4µs PHY_ON CMD_PHY_ON 55.4µs ...
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... The required preamble length depends on the radio configuration. See the Radio Blocks section for more details. In receive mode, the ADF7023-J can use a preamble qualification circuit to detect preamble and interrupt the host processor. The preamble qualification circuit tracks the received frame as a sliding window ...
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... Figure 53 and Table 18. In receive mode, the ADF7023-J can provide an interrupt on reception of the sync word sequence programmed in the SYNC_BYTE_0, SYNC_BYTE_1, and SYNC_BYTE_2 registers. This feature can be used to alert the host processor that a qualified sync word has been received ...
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... The same orientation setting should be used on the transmit and receive sides of the RF link. Packet Length Modes The ADF7023-J can be used in both fixed and variable length packet systems. Fixed or variable length packet mode is set using the PACKET_LEN variable setting in the PACKET_ LENGTH_CONTROL register (Address 0x126) ...
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... The system also uses broadcast addresses in which the first byte is always 0xAA. To match the exact address, 0xABCDEF01 or any broadcast address in the form 0xAAXXXXXX, the ADF7023-J must be configured as shown in Table 20. Table 20. Example Address Check Configuration BBRAM ...
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... ADF7023-J To convert a user-defined polynomial to the 2-byte value, the polynomial should be written in binary format. The x is assumed equal to 1 and is, therefore, discarded. The remaining 16 bits then make up CRC_POLY_0 (most significant byte) and CRC_POLY_1 (least significant byte). Two examples of setting common 16-bit CRCs are shown in Table 22. ...
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... Manchester encoding. The rate loss for 8b/10b encoding is 0.8, whereas for Manchester encoding 0.5. Encoding and decoding are applied to the payload data and the CRC. The 8b/10b encoding and decoding are enabled by setting EIGHT_TEN_ENC =1 in the SYMBOL_MODE register (Address 0x11C). Rev Page 43 of 100 ADF7023-J ...
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... ADF7023-J INTERRUPT GENERATION The ADF7023-J uses a highly flexible, powerful interrupt system with support for MAC level interrupts and PHY level interrupts. To enable an interrupt source, the corresponding mask bit must be set. When an enabled interrupt occurs, the IRQ_GP3 pin goes high, and the interrupt bit of the status word is set to Logic 1 ...
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... Address 0x108) Asserted when an AES encryption or decryption command is complete; available only when the AES firmware module has been loaded to the ADF7023-J program RAM Asserted when a packet has finished transmitting (packet mode only) Asserted when a received packet has a valid address match (packet ...
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... ADF7023-J INTERRUPTS IN SPORT MODE In sport mode, the interrupts from INTERRUPT_SOURCE_1 are all available. However, only INTERRUPT_PREAMBLE_DETECT and INTERRUPT_SYNC_DETECT are available from INTERRUPT_SOURCE_0. A second interrupt pin is provided on GP4, which gives a dedicated sport mode interrupt on either preamble or sync word detection. For more details, see the Sport Mode section ...
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... The battery backup RAM contains the main radio and packet management registers used to configure the radio. On application of battery power to the ADF7023-J for the first time, the entire BBRAM should be initialized by the host processor with the appropriate settings. After the BBRAM is written to, the ...
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... ADF7023-J PACKET RAM The packet RAM consists of 256 bytes of memory space. The first 16 bytes of this memory space are allocated for use by the on-chip processor. The remaining 240 bytes of this memory space are allocated for storage of data from valid received packets and packet data to be transmitted. The communications processor ...
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... SPI INTERFACE GENERAL CHARACTERISTICS The ADF7023-J is equipped with a 4-wire SPI interface, using the SCLK, MISO, MOSI, and CS pins. The ADF7023-J always acts as a slave to the host processor. Figure 59 connection diagram between the processor and the ADF7023-J. The diagram also shows the direction of the signal flow for each pin ...
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... CMD_READY FW_STATE = 0x11 (PHY_OFF) 0xB1 STATUS WORD COMMUNICATIONS WAITING FOR COMMAND PROCESSOR ACTION Figure 62. Operation of the CMD_READY and FW_STATE Bits in Transitioning the ADF7023-J from the PHY_OFF State to the PHY_ON State CS CMD_READY FW_STATE = 0x11 (PHY_OFF) STATUS WORD 0xB1 COMMUNICATIONS WAITING FOR COMMAND PROCESSOR ACTION Figure 63 ...
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... Table 27). An SPI command should be issued only if the SPI_READY bit in the INTERRUPT_SOURCE_1 register (Address 0x337) of the status word bit is high. The ADF7023-J interrupt handler can also be configured to generate an interrupt signal on IRQ_GP3 when the SPI_READY bit is high. ...
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... ADF7023-J Random Address Write MCR, BBRAM, and packet RAM memory locations can be written nonsequential manner using the SPI_MEMR_WR command. The SPI_MEMR_WR command code is 00001xxxb, where xxxb represent Bits[10:8] of the 11-bit address. The lower eight bits of the address should follow this command and then the data byte to be written to the address ...
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... Figure 67. Memory (MCR, BBRAM, or Packet RAM) Block Read ADDRESS 2 ADDRESS 3 ADDRESS 4 DATA FROM DATA FROM STATUS ADDRESS 1 ADDRESS 2 Rev Page 53 of 100 MAX N = (256-INITIAL ADDRESS) SPI_NOP SPI_NOP DATA FROM DATA FROM ADDRESS + 1 ADDRESS + N ADDRESS N SPI_NOP SPI_NOP DATA FROM DATA FROM DATA FROM ADDRESS N – 2 ADDRESS N – 1 ADDRESS N ADF7023-J ...
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... The 32.768 kHz RCOSC or XOSC provides the clock source for the timer. The firmware timer is a software timer residing on the ADF7023-J. The firmware timer is used to count the number of WUC timeouts and can be used to count the number of ADF7023-J wake-ups. ...
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... SWM_RSSI_THRESH[7:0] RSSI threshold for RSSI prequalification. RSSI threshold (dBm) = SWM_RSSI_THRESH − 107. PARMTIME_DIVIDER[7:0] Tick rate for the Rx dwell timer. RX_DWELL_TIME[7:0] Time that the ADF7023-J remains awake during SWM. Receive Dwell Time = RX_DWELL_TIME × 128 INTERRUPT_SWM_RSSI_DET Various interrupts that can be used in INTERRUPT_PREAMBLE_DETECT SWM ...
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... ADF7023-J MEASURE RSSI NO RSSI > THRESHOLD (SWM_RSSI_THRESH) YES RSSI INT ENABLED? (INTERRUPT_ SWM_RSSI_DET) NO RX_DWELL_TIME EXCEEDED ADF7023-J PHY_SLEEP NO BBRAM RETAINED? YES NO WUC CONFIGURED? YES INCREMENT NUMBER_OF_WAKEUPS NUMBER_OF_WAKEUPS YES > THRESHOLD? NO SWM ENABLED? NO (SWM_EN = 1) YES YES RSSI QUAL ENABLED? (SWM_RSSI_QUAL) NO YES YES PREAMBLE DETECTED? NO AND ...
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... Deep Sleep Mode 1 is suitable for applications where the host processor controls the low power mode timing and the ADF7023-J configuration is retained during the PHY_SLEEP state. In this low power mode, the ADF7023 the PHY_SLEEP state with the BBRAM contents retained. Before entering the PHY_SLEEP state, the WUC_BBRAM_EN bit (Address 0x30D) should be set ensure that the BBRAM is retained ...
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... When RSSI prequalification is enabled, the ADF7023-J begins searching for the preamble only if the RSSI measurement is greater than the user-defined threshold. The ADF7023 the PHY_RX state for a duration deter- mined by the RX_DWELL_TIME setting (Address 0x106). If the ADF7023-J detects the preamble during the receive dwell time, it searches for the sync word ...
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... PHY_SLEEP RX PHY_SLEEP WUC TIMEOUT PERIOD Rev Page 59 of 100 PHY_SLEEP PHY_OFF INCREMENT FIRMWARE TIMER FIRMWARE TIMER > THRESHOLD PHY_SLEEP PHY_OFF RSSI ≤ THRESHOLD RSSI > THRESHOLD RSSI PHY_SLEEP RSSI NO PACKET PACKET DETECTED DETECTED RX PHY_SLEEP INIT PHY_RX RECEIVE DWELL TIME (RX_DWELL_TIME) ADF7023-J PHY_ON PHY_ON ...
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... ADF7023-J WUC SETUP Circuit Description The ADF7023-J features a low power wake-up controller comprising a 16-bit wake-up timer with a 3-bit programmable prescaler, as illustrated in Figure 74. The prescaler clock source can be configured to use either the 32.76 kHz internal RC oscillator (RCOSC) or the 32.76 kHz external oscillator (XOSC). This combination of programmable prescaler and 16-bit down counter gives a total hardware timer range of 30.52 μ ...
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... WUC_CONFIG_LOW [3] WUC_CONFIG_LOW[2:1] WUC_CONFIG_LOW[0] FIRMWARE TIMER SETUP The ADF7023-J wakes up from the PHY_SLEEP state at the rate set by the WUC. A firmware timer, implemented by the on-chip processor, can be used to count the number of hardware wake-ups and generate an interrupt to the host processor. Thus, the ADF7023-J can be used to handle the wake-up timing of the host processor, reducing overall system power consumption ...
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... ADF7023-J DOWNLOADABLE FIRMWARE MODULES The program RAM memory of the ADF7023-J can be used to store firmware modules for the communications processor that provide the ADF7023-J with extra functionality. The binary code for these firmware modules and details on their functionality are available from Analog Devices. These firmware modules are included in the Applications Software, which is available online at ftp://ftp ...
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... AES AES ENCRYPT ENCRYPT 128 BITS 128 BITS Figure 76. ECB Mode CBC MODE 1 128 BITS 128 BITS + + KEY KEY AES AES ENCRYPT ENCRYPT 128 BITS 128 BITS Figure 77. CBC Mode 1 Rev Page 63 of 100 ADF7023-J 128 BITS + AES ENCRYPT 128 BITS ...
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... RADIO_CFG_9 register (Address 0x115). The Gaussian filter uses a bandwidth time (BT) of 0.5. The VCO and the PLL loop filter of the ADF7023-J are fully integrated. To reduce the effect of pulling of the VCO by the power-up of the PA and to minimize spurious emissions, the VCO operates at twice the RF frequency ...
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... Their values are dependent upon the crystal specification. They should be chosen to ensure that the shunt value of capacitance added to the PCB track capacitance and the input pin capacitance of the ADF7023-J equals the specified load capacitance of the crystal, usually pF. Track capacitance values vary from pF, depending on board layout ...
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... PA configurations offer a Tx antenna diversity capability. Note that the two PAs cannot be enabled at the same time. Automatic PA Ramp The ADF7023-J has built-in up and down PA ramping for both single-ended and differential PAs. There are eight ramp rate settings, with the ramp rate defined as a certain number of PA power level settings per data bit period ...
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... The analog RSSI level is digitized by an 8-bit SAR ADC for user readback and for use by the digital AGC controller. The ADF7023-J has three RSSI measurement functions that support a wide range of applications. These functions can be used to implement carrier sense (CS) or clear channel assessment (CCA) ...
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... ADF7023-J Table 36. Summary of RSSI Measurement Methods RSSI Method RSSI Type Modulation 1 Automatic end of 2FSK/GFSK/ packet RSSI MSK/GMSK 2 CMD_GET_RSSI 2FSK/GFSK/ command from MSK/GMSK PHY_ON 3 RSSI via ADC and 2FSK/GFSK/ AGC readback, FSK MSK/GMSK Available in Available in Packet Mode Sport Mode Description Yes No Automatic RSSI measurement during reception of the postamble in packet mode ...
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... Gaussian noise (AWGN). This method of 2FSK/GFSK/MSK/ GMSK demodulation provides approximately better sensitivity than a linear frequency discriminator. The 2FSK/GFSK/ MSK/GMSK demodulator architecture is shown in Figure 80. The ADF7023-J is configured for 2FSK/GFSK/MSK/GMSK demodulation by setting DEMOD_SCHEME = 0 in the RADIO_CFG_9 register (Address 0x115). To optimize receiver sensitivity, the correlator bandwidth and ...
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... Even Odd Odd AFC The ADF7023-J features an internal real-time automatic frequency control loop. In receive mode, the control loop automatically monitors the frequency error during the packet preamble sequence and adjusts the receiver synthesizer local oscillator using proportional integral (PI) control. The AFC frequency error measurement bandwidth is targeted specifically at the packet preamble sequence (dc free) ...
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... More details of CDR operation using uncoded packet formats are discussed in the AN-915 Application Note. The CDR PLL of the ADF7023-J is optimized for fast acquisition of the recovered symbols during preamble and typically achieves bit synchronization within five symbol transitions of preamble. RECOMMENDED RECEIVER SETTINGS FOR ...
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... ADF7023-J Table 41. Summary of Recommended AGC, AFC, Preamble Length, and Sync Word Error Tolerance for 2FSK/GFSK/MSK/GMSK AFC Data Frequency IF Pull-In Rate Deviation BW Range (kbps) (kHz) (kHz) (kHz) 300 75 300 ±150 200 50 200 ±100 150 37.5 150 ±75 100 25 100 ±50 50 12.5 100 ± ...
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... PERIPHERAL FEATURES ANALOG-TO-DIGITAL CONVERTER The ADF7023-J supports an integrated SAR ADC for digitization of analog signals that include the analog temperature sensor, the analog RSSI level, and an external analog input signal (Pin 30). The conversion time is typically 1 μs. The result of the conversion can be read from the ADC_READBACK_HIGH register (Address 0x327), and the ADC_READBACK_LOW register (Address 0x328) ...
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... ADF7023-J occurs on the SPI interface and the IRQ_GP3 pin. The interface between the ADF7023-J and the host processor in sport mode is shown in Figure 82. In sport mode, the transmit and receive data interface consists of the GP0, GP1, and GP2 pins and a separate interrupt is available on GP4, while the SPI interface is used for memory access and issuing of commands ...
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... PA/LNA MATCHING The ADF7023-J has a differential LNA and both a single-ended PA and differential PA. This flexibility allows numerous possibilities in interfacing the ADF7023-J to the antenna. Combined Single-Ended PA and LNA Match The combined single-ended PA and LNA match allows the transmit and receive paths to be combined without the use of an external transmit/receive switch ...
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... PHY_TX state and logic low while in any other state. If the EXT_LNA_EN bit is set the MODE_CONTROL register (Address 0x11A), the external LNA control signal is logic high while the ADF7023 the PHY_RX state and logic low while in any other state. DIFFERENTIAL PA AND LNA MATCH ...
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... SPI_NOP commands. Writes data to BBRAM, MCR, or packet RAM memory nonsequentially. Reads data from BBRAM, MCR, or packet RAM memory nonsequentially. No operation. Use for dummy writes when polling the status word; used also as dummy data when performing a memory read. Rev Page 77 of 100 ADF7023-J ...
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... ADF7023-J REGISTER MAPS Table 47. Battery Backup Memory (BBRAM) Address (Hex) Register 0x100 INTERRUPT_MASK_0 0x101 INTERRUPT_MASK_1 0x102 NUMBER_OF_WAKEUPS_0 0x103 NUMBER_OF_WAKEUPS_1 0x104 NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_0 0x105 NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_1 0x106 RX_DWELL_TIME 0x107 PARMTIME_DIVIDER 0x108 SWM_RSSI_THRESH 0x109 CHANNEL_FREQ_0 0x10A CHANNEL_FREQ_1 0x10B CHANNEL_FREQ_2 0x10C RADIO_CFG_0 0x10D RADIO_CFG_1 0x10E RADIO_CFG_2 ...
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... VCO_AMPL_READBACK 0x3F8 ANALOG_TEST_BUS 0x3F9 RSSI_TSTMUX_SEL 0x3FA GPIO_CONFIGURE 0x3FD TEST_DAC_GAIN Retained in PHY_SLEEP Rev Page 79 of 100 ADF7023-J R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W ...
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... RSSI threshold value (SWM_RSSI_THRESH, Address 0x108) 1: interrupt enabled; 0: interrupt disabled R/W Interrupt when an AES encryption or decryption command is complete; available only when the AES firmware module has been loaded to the ADF7023-J program RAM 1: interrupt enabled; 0: interrupt disabled R/W Interrupt when a packet has finished transmitting 1: interrupt enabled ...
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... This sets the RSSI threshold when in smart wake mode with RSSI detection enabled. Threshold (dBm) = SWM_RSSI_THRESH − 107 R/W Description R/W The RF channel frequency in hertz is set according to ( CHANNEL_FR = × Frequency (Hz) f PFD where f is the PFD frequency and is equal to 26 MHz. PFD Rev Page 81 of 100 ADF7023-J IVIDER 6.5 MHz EQ[ ...
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... ADF7023-J Table 60. 0x10A: CHANNEL_FREQ_1 Bit Name [7:0] CHANNEL_FREQ[15:8] Table 61. 0x10B: CHANNEL_FREQ_2 Bit Name [7:0] CHANNEL_FREQ[23:16] Table 62. 0x10C: RADIO_CFG_0 Bit Name R/W [7:0] DATA_RATE[7:0] R/W Table 63. 0x10D: RADIO_CFG_1 Bit Name [7:4] FREQ_DEVIATION[11:8] [3:0] DATA_RATE[11:8] Table 64. 0x10E: RADIO_CFG_2 Bit Name [7:0] FREQ_DEVIATION[7:0] Table 65. 0x10F: RADIO_CFG_3 ...
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... LUT for transmit must be reloaded to packet RAM after waking from the PHY_SLEEP state. R/W If SYNTH_LUT_CONTROL = set SYNTH_LUT_CONFIG_0 SYNTH_LUT_CONTROL = this setting allows the receiver PLL loop bandwidth to be changed to optimize the receiver local oscillator phase noise. PA Single-ended PA enabled Differential PA enabled PA Level (PA_LEVEL_MCR) Setting 3 Setting 7 Setting 11 Setting 63 Rev Page 83 of 100 ADF7023-J ...
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... ADF7023-J Bit Name R/W Description [2:0] PA_RAMP R/W Sets the PA ramp rate. The PA ramps at the programmed rate until it reaches the level indicated by the PA_LEVEL_MCR (Address 0x307) setting. The ramp rate is dependent on the programmed data rate. PA_RAMP ensure the correct PA ramp-up and ramp-down timing, the PA ramp rate has a minimum value based on the data rate and the PA_LEVEL or PA_LEVEL_MCR settings ...
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... R/W 1: external LNA enable signal on ATB4 is enabled. The signal is logic high while the ADF7023 the PHY_RX state and logic low while in any other nonsleep state. 0: external LNA enable signal on ATB4 is disabled. R/W 1: external PA enable signal on ATB3 is enabled. The signal is logic high while the ADF7023 the PHY_TX state and logic low while in any other nonsleep state ...
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... ADF7023-J Table 77. 0x11B: PREAMBLE_MATCH Bit Name [7] EXT_PA_LNA_CONFIG [6:4] Reserved [3:0] PREAMBLE_MATCH Table 78. 0x11C: SYMBOL_MODE Bit Name [7] Reserved [6] MANCHESTER_ENC [5] PROG_CRC_EN [4] EIGHT_TEN_ENC [3] DATA_WHITENING [2:0] SYMBOL_LENGTH Table 79. 0x11D: PREAMBLE_LEN Bit Name [7:0] PREAMBLE_LEN Table 80. 0x11E: CRC_POLY_0 Bit Name [7:0] CRC_POLY[7:0] Table 81. 0x11F: CRC_POLY_1 Bit ...
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... R/W Address in packet RAM of the receive packet. The communications processor writes any qualified received packet to packet RAM, starting at this memory location. Rev Page 87 of 100 ADF7023-J Bit Error Tolerance 0 bit errors allowed. One bit error allowed. Two bit errors allowed. Three bit errors allowed. ...
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... RAM mode, the packet length is given by PACKET_LENGTH_MAX. R/W 1: append CRC in transmit mode. Check CRC in receive mode CRC addition in transmit mode. No CRC check in receive mode. R/W Sets the ADF7023-J to packet mode or sport mode for transmit and receive data. DATA_MODE Description 0 Packet mode enabled. 1 Sport mode enabled ...
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... R/W Description R/W The ADF7023-J has the ability to implement automatic static register fixes from BBRAM memory to MCR memory. This feature allows a maximum of nine MCR registers to be programmed via BBRAM memory. This feature is useful if MCR registers must be configured for optimum receiver performance in low power mode ...
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... ADF7023-J MCR REGISTER DESCRIPTION The MCR register settings are not retained when the device enters the PHY_SLEEP state. Table 96. 0x307: PA_LEVEL_MCR Bit Name [5:0] PA_LEVEL_MCR Table 97. 0x30C: WUC_CONFIG_HIGH Bit Name [7] Reserved [6] WUC_BGAP [5] WUC_LDO_SYNTH [4] WUC_LDO_DIG [3] WUC_XTO26M_EN [2:0] WUC_PRESCALER Register WUC_CONFIG_LOW should never be written to without updating Register WUC_CONFIG_HIGH first. ...
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... Reset Description R/W 50 Limits the AFC pull-in range. Automatically set by the communications processor on transitioning into the PHY_RX state. The range is set equal to half the IF bandwidth. Example: IF bandwidth = 200 kHz, AFC pull-in range = ±100 kHz (MAX_AFC_RANGE = 100). Rev Page 91 of 100 ADF7023-J ...
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... ADF7023-J Table 105. 0x319: IMAGE_REJECT_CAL_CONFIG Bit Name [7:6] Reserved [5] IMAGE_REJECT_CAL_OVWRT_EN [4:3] IMAGE_REJECT_FREQUENCY [2:0] IMAGE_REJECT_POWER Table 106. 0x322: CHIP_SHUTDOWN Bit Name [7:1] Reserved [0] CHIP_SHTDN_REQ Table 107. 0x324: POWERDOWN_RX Bit Name [7:5] Reserved [4] ADC_PD_N [3] RSSI_PD_N [2] RXBBFILT_PD_N [1] RXMIXER_PD_N [0] LNA_PD_N Table 108. 0x325: POWERDOWN_AUX Bit ...
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... RSSI threshold value (SWM_RSSI_THRESH, Address 0x108) R/W 0 Asserted when an AES encryption or decryption command is complete; available only when the AES firmware module has been loaded to the ADF7023-J program RAM R/W 0 Asserted when a packet has finished transmitting (packet mode only) R/W ...
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... ADF7023-J Table 116. 0x338: CALIBRATION_CONTROL Bit Name [7:2] Reserved [1] SYNTH_CAL_EN [0] RXBB_CAL_EN Table 117. 0x339: CALIBRATION_STATUS Bit Name [7:3] Reserved [2] PA_RAMP_FINISHED [1] SYNTH_CAL_READY [0] RXBB_CAL_READY Table 118. 0x345: RXBB_CAL_CALWRD_READBACK Bit Name [5:0] RXBB_CAL_CALWRD Table 119. 0x346: RXBB_CAL_CALWRD_OVERWRITE Bit Name [6:1] RXBB_CAL_DCALWRD_OVWRT_IN [0] RXBB_CAL_DCALWRD_OVWRT_EN Table 120. 0x359: ADC_CONFIG_LOW ...
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... Reset Description low 1: medium 2: high 3: reserved low 1: high low 1: medium 2: high 3: reserved R/W Reset Description R 0 Frequency error between received signal frequency and receive channel frequency = FREQUENCY_ERROR_READBACK × 1 kHz. The FREQUENCY_ERROR_READBACK value is in twos complement format. Rev Page 95 of 100 ADF7023-J ...
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... ADF7023-J Table 128. 0x3CB: VCO_BAND_OVRW_VAL Bit Name [7:0] VCO_BAND_OVRW_VAL Table 129. 0x3CC: VCO_AMPL_OVRW_VAL Bit Name [7:0] VCO_AMPL_OVRW_VAL Table 130. 0x3CD: VCO_OVRW_EN Bit Name [7:6] Reserved [5:2] VCO_Q_AMP_REF [1] VCO_AMPL_OVRW_EN [0] VCO_BAND_OVRW_EN Table 131. 0x3D0: VCO_CAL_CFG Bit Name [7:4] Reserved [3:0] VCO_CAL_CFG Table 132. 0x3D2: OSC_CONFIG ...
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... Test DAC output on GP0 (also must set TEST_DAC_GAIN) R/W Reset Description R/W 0 Reserved R/W 4 Set TEST_DAC_GAIN = 0 when using the test DAC Mode Default; no transmit test mode Reserved Transmit the preamble continuously Transmit the carrier continuously Reserved Rev Page 97 of 100 ADF7023-J ...
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... ADF7023-J OUTLINE DIMENSIONS PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADF7023-JBCPZ −40°C to +85°C ADF7023-JBCPZ-RL −40°C to +85°C EVAL-ADF7XXXMB3Z EVAL-ADF7023-JDB1Z EVAL-ADF7023-JDB2Z RoHS Compliant Part. 5.10 0.30 5.00 SQ 0.25 4.90 0. 0.50 BSC 17 16 0.50 TOP VIEW BOTTOM VIEW 0 ...
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... NOTES Rev Page 99 of 100 ADF7023-J ...
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... ADF7023-J NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09555-0-5/11(0) Rev Page 100 of 100 ...