ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 65

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Synthesizer Settling
After the VCO calibration, a 56 μs delay is allowed for synthesizer
settling. This delay is fixed at 56 μs by default and ensures that
the synthesizer has fully settled when using any of the default
synthesizer bandwidths.
However, in some cases, it may be necessary to use a custom
synthesizer settling delay. To use a custom delay, set the CUSTOM_
TRX_SYNTH_LOCK_TIME EN bit to 1 in the MODE_CONTROL
register (Address 0x11A). The synthesizer settling delays for the
PHY_RX and the PHY_TX state transitions can be set independently
in the RX_SYNTH_LOCK_TIME register (Address 0x13E) and
the TX_SYNTH_LOCK_TIME register (Address 0x13F). The
settling time can be set in the 2 μs to 512 μs range in steps of 2 μs.
Bypassing VCO Calibration
It is possible to bypass the VCO calibration for ultrafast frequency
hopping in transmit or receive. The calibration data for each RF
channel should be stored in the host processor memory. The
calibration data comprises two values: the VCO band select
value and the VCO amplitude level.
Read and Store Calibration Data
1.
2.
Bypassing VCO Calibration on CMD_PHY_TX or
CMD_PHY_RX
1.
2.
3.
4.
5.
6.
7.
8.
CRYSTAL OSCILLATOR
A 26 MHz crystal oscillator operating in parallel mode must be
connected between the XOSC26P and XOSC26N pins. Two
parallel loading capacitors are required for oscillation at the
correct frequency. Their values are dependent upon the crystal
specification. They should be chosen to ensure that the shunt
value of capacitance added to the PCB track capacitance and the
input pin capacitance of the ADF7023-J equals the specified
Go to the PHY_TX or the PHY_RX state without bypassing
the VCO calibration.
Read the following MCR registers and store the calibrated
data in memory on the host processor:
a.
b.
Ensure that the BBRAM is configured.
Set VCO_OVRW_EN (Address 0x3CD) = 0x3.
Set VCO_CAL_CFG (Address 0x3D0) = 0x0F.
Set VCO_BAND_OVRW_VAL (Address 0x3CB) = stored
VCO_BAND_READBACK (Address 0x3DA) for that
channel.
Set VCO_AMPL_OVRW_VAL (Address 0x3CC) = stored
VCO_AMPL_READBACK (Address 0x3DB) for that
channel.
Set SYNTH_CAL_EN = 0 (in the CALIBRATION_
CONTROL register, Address 0x338).
Set SYNTH_CAL_EN = 1 (in the CALIBRATION_
CONTROL register, Address 0x338).
Issue CMD_PHY_TX or CMD_PHY_RX to go to the
PHY_TX or PHY_RX state without the VCO calibration.
VCO_BAND_READBACK (Address 0x3DA)
VCO_AMPL_READBACK (Address 0x3DB)
Rev. 0 | Page 65 of 100
load capacitance of the crystal, usually 10 pF to 20 pF. Track
capacitance values vary from 2 pF to 5 pF, depending on board
layout. The total load capacitance is described by
where:
C
C1 and C2 are the external crystal load capacitors.
C
XOSC26N pins and is equal to 2.1 pF.
C
When possible, choose capacitors that have a very low
temperature coefficient to ensure stable frequency operation
over all conditions.
The crystal frequency error can be corrected by means of an
integrated digital tuning varactor. For a typical crystal load
capacitance of 10 pF, a tuning range of −15 ppm to +11.25 ppm
is available via programming of a 3-bit DAC, according to Table 32.
The 3-bit value should be written to the XOSC_CAP_DAC bits
in the OSC_CONFIG register (Address 0x3D2).
Alternatively, any error in the RF frequency due to crystal error
can be adjusted for by offsetting the RF channel frequency using
the RF channel frequency setting in BBRAM memory.
Table 32. Crystal Frequency Pulling Programming
XOSC_CAP_DAC
000
001
010
011
100
101
110
111
MODULATION
The ADF7023-J supports binary frequency shift keying (2FSK),
minimum shift keying (MSK), binary level Gaussian filtered
2FSK (GFSK), and Gaussian filtered MSK (GMSK). The desired
transmit and receive modulation formats are set in the
RADIO_CFG_9 register (Address 0x115).
When using 2FSK/GFSK/MSK/GMSK modulation, the frequency
deviation can be set using the FREQ_DEVIATION[11:0] bits
in the RADIO_CFG_1 register (Address 0x10D) and the
RADIO_CFG_2 register (Address 0x10E). The data rate can be
set in the 1 kbps to 300 kbps range using the DATA_RATE[11:0]
parameter in the RADIO_CFG_0 register (Address 0x10C) and
RADIO_CFG_1 register (Address 0x10D). For GFSK/GMSK
modulation, the Gaussian filter uses a fixed BT of 0.5.
LOAD
PIN
PCB
is the ADF7023-J input capacitance of the XOSC26P and
is the PCB track capacitance.
C
is the total load capacitance.
LOAD
=
C1
1
+
1
C2
1
+
C
PIN
2
Pulling (ppm)
+15
+11.25
+7.5
+3.75
0
−3.75
−7.5
−11.25
+
C
PCB
ADF7023-J