ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 29

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

INITIALIZATION
Initialization After Application of Power
When power is applied to the ADF7023-J (through the
VDDBAT1/VDDBAT2 pins), it registers a power-on reset
(POR) event and transitions to the PHY_OFF state. The
BBRAM memory is unknown, the packet RAM memory is
cleared to 0x00, and the MCR memory is reset to its default
values. The host processor should use the following procedure
to complete the initialization sequence:
1.
2.
3.
4.
5.
The ADF7023-J is now configured in the PHY_OFF state.
Initialization After Issuing the CMD_HW_RESET
Command
The CMD_HW_RESET command performs a full power-down
of all hardware, and the device enters the PHY_SLEEP state. To
complete the hardware reset, the host processor should
complete the following procedure:
1.
2.
3.
4.
5.
6.
The ADF7023-J is now configured in the PHY_OFF state.
Bring the CS pin of the SPI low and wait until the MISO
output goes high.
Issue the CMD_SYNC command.
Wait for the CMD_READY bit in the status word to go high.
Configure the part by writing to all 64 of the BBRAM
registers.
Issue the CMD_CONFIG_DEV command so that the
radio settings are updated using the BBRAM values.
Wait for 1 ms.
Bring the CS pin of the SPI low and wait until the MISO
output goes high. The ADF7023-J registers a POR and
enters the PHY_OFF state.
Issue the CMD_SYNC command.
Wait for the CMD_READY bit in the status word to go high.
Configure the part by writing to all 64 of the BBRAM registers.
Issue the CMD_CONFIG_DEV command so that the
radio settings are updated using the BBRAM values.
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Initialization on Transitioning from PHY_SLEEP (After CS
Is Brought Low)
The host processor can bring CS low at any time to wake the
ADF7023-J from the PHY_SLEEP state. This event is not
registered as a POR event because the BBRAM contents are
valid. The following is the procedure that the host processor is
required to follow:
1.
2.
3.
4.
The ADF7023-J is now configured and ready to transition to
the PHY_ON state.
Initialization After a WUC Timeout
The ADF7023-J can autonomously wake from the PHY_SLEEP
state using the wake-up controller. If the ADF7023-J wakes after
a WUC timeout in smart wake mode (SWM), it follows the SWM
routine based on the smart wake mode configuration in BBRAM
(see the Low Power Modes section). If the ADF7023-J wakes
after a WUC timeout with SWM disabled and the firmware
timer disabled, it wakes in the PHY_OFF state, and the following
is the procedure that the host processor is required to follow:
1.
2.
3.
The ADF7023-J is now configured in the PHY_OFF state.
Bring the CS line of the SPI low and wait until the MISO
output goes high. The ADF7023-J enters the PHY_OFF state.
Issue the CMD_SYNC command.
Wait for the CMD_READY bit in the status word to go high.
Issue the CMD_CONFIG_DEV command so that the
radio settings are updated using the BBRAM values.
Issue the CMD_SYNC command.
Wait for the CMD_READY bit in the status word to go high.
Issue the CMD_CONFIG_DEV command so that the
radio settings are updated using the BBRAM values.
ADF7023-J