ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 89

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 90. 0x128: STATIC_REG_FIX
Bit
[7:0]
Table 91. 0x129: ADDRESS_MATCH_OFFSET
Bit
[7:0]
Table 92. 0x12A: ADDRESS_LENGTH
Bit
[7:0]
Table 93. 0x12B to 0x13D: Address Matching
Address
0x12B
0x12C
0x12D
0x12E
…
Table 94. 0x13E: RX_SYNTH_LOCK_TIME
Bit
[7:0]
Table 95. 0x13F: TX_SYNTH_LOCK_TIME
Bit
[7:0]
Name
RX_SYNTH_LOCK_TIME
Name
TX_SYNTH_LOCK_TIME
Name
STATIC_REG_FIX
Name
ADDRESS_MATCH_OFFSET
Name
ADDRESS_LENGTH
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Allows the use of a custom synthesizer lock time counter in transmit mode in
conjunction with the CUSTOM_TRX_SYNTH_LOCK_TIME_EN setting in the
MODE_CONTROL register. Applies after VCO calibration is complete. Each bit
equates to a 2 μs increment.
Rev. 0 | Page 89 of 100
Description
The ADF7023-J has the ability to implement automatic static register fixes
from BBRAM memory to MCR memory. This feature allows a maximum of
nine MCR registers to be programmed via BBRAM memory. This feature is
useful if MCR registers must be configured for optimum receiver performance in
low power mode. The STATIC_REG_FIX value is an address pointer to any
BBRAM memory address between 0x12A and 0x13D. For example, to point
to BBRAM Address 0x12B, set STATIC_REG_FIX = 0x2B.
•
•
Example: write 0x46 to MCR Register 0x35E and write 0x78 to
MCR Register 0x35F. Set STATIC_REG_FIX = 0x2B.
BBRAM Register
0x128 (STATIC_REG_FIX)
0x12B
0x12C
0x12D
0x12E
0x12F
Description
Location of first byte of address information in packet RAM
Description
Number of bytes in the first address field (N
matching is not being used.
Description
Address 1 Match Byte 0.
Address 1 Mask Byte 0.
Address 1 Match Byte 1.
Address 1 Mask Byte 1.
…
Address 1 Match Byte N
Address 1 Mask Byte N
0x00 to end or number of bytes in the second address field (N
Description
Allows the use of a custom synthesizer lock time counter in receive mode in
conjunction with the CUSTOM_TRX_SYNTH_LOCK_TIME_EN setting in the
MODE_CONTROL register. Applies after VCO calibration is complete. Each
bit equates to a 2 μs increment.
If STATIC_REG_FIX = 0x00, then static register fixes are disabled.
If STATIC_REG_FIX is nonzero, the communications processor looks for
the MCR address and corresponding data at the BBRAM address
beginning at STATIC_REG_FIX.
ADR_1
ADR_1
0x2B
.
Data
0x5E
0x46
0x5F
0x78
0x00
.
Pointer to BBRAM Address 0x12B
Description
MCR Address 1
Data to write to MCR Address 1
MCR Address 2
Data to write to MCR Address 2
Ends static MCR register fixes
ADR_1
). Set to zero if address
ADF7023-J
ADR_2
).