ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 67

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The AGC remains at each gain stage for a time defined by the
AGC_CLK_DIVIDE register (Address 0x32F). The default
value of AGC_CLK_DIVIDE = 0x28 gives an AGC delay of
25 μs. When the RSSI is above AGC_HIGH_THRESHOLD
(Address 0x35F), the gain is reduced. When the RSSI is below
AGC_LOW_THRESHOLD (Address 0x35E), the gain is increased.
The AGC can be configured to remain active while in the PHY_RX
state or can be locked on preamble detection. The AGC can also
be set to manual mode, in which case, the host processor must
set the LNA, filter, and mixer gains by writing to the AGC_MODE
register (Address 0x35D). The AGC operation is set by the
AGC_LOCK_MODE setting in the RADIO_CFG_7 register
(Address 0x113) and is described in Table 34.
The LNA, filter, and mixer gains can be read back through the
AGC_GAIN_STATUS register (Address 0x360).
Table 34. AGC Operation
AGC_LOCK_MODE Bits
in RADIO_ CFG_7 Register
0
1
2
3
RSSI
The RSSI is based on a successive compression, log amplifier
architecture following the analog channel filter. The analog
RSSI level is digitized by an 8-bit SAR ADC for user readback
and for use by the digital AGC controller.
The ADF7023-J has three RSSI measurement functions that
support a wide range of applications. These functions can be
used to implement carrier sense (CS) or clear channel assessment
(CCA). In packet mode, the RSSI is automatically recorded in MCR
memory and is available for user readback after receipt of a packet.
Table 36 details the three RSSI measurement methods.
RSSI Method 1
When a valid packet is received in packet mode, the RSSI level
during postamble is automatically loaded to the RSSI_READBACK
register (Address 0x312) by the communications processor. The
RSSI_READBACK register contains a twos complement value and
can be converted to input power in dBm using the following
formula:
To extend the linear range of RSSI measurement down to an
input power of −110 dBm (see Figure 42), a cosine adjustment
can be applied using the following formula:
where COS(X) is the cosine of angle X (radians).
RSSI(dBm) = RSSI_READBACK − 107
RSSI(dBm) =
COS
⎛
⎜
⎝
RSSI _
READBACK
8
Description
AGC is free running.
AGC is disabled. Gains must be set
manually.
AGC is held at the current gain level.
AGC is locked on preamble detection.
⎞
⎟
⎠
× RSSI_READBACK − 106
Rev. 0 | Page 67 of 100
RSSI Method 2
The CMD_GET_RSSI command can be used from the PHY_ON
state to read the RSSI. This RSSI measurement method uses
additional low-pass filtering, resulting in a more accurate RSSI
reading. The RSSI result is loaded to the RSSI_READBACK
register (Address 0x312) by the communications processor.
The RSSI_READBACK register contains a twos complement
value and can be converted to input power in dBm using the
following formula:
The CMD_GET_RSSI execution time is specified in Table 11.
RSSI Method 3
This method supports the measurement of RSSI by the host
processor at any time while in the PHY_RX state. The receiver
input power can be calculated using the following procedure:
1.
2.
3.
4.
5.
Table 35. Gain Mode Correction for 2FSK/GFSK/MSK/GMSK
RSSI
To simplify the RSSI calculation, the following approximation
can be used by the host processor:
AGC_GAIN_STATUS
(Address 0x360)
0x00
0x01
0x02
0x0A
0x12
0x16
RSSI(dBm) = RSSI_READBACK – 107
Set AGC to hold by setting the AGC_MODE register
(Address 0x35D) = 0x40 (only necessary if AGC has not
been locked on the preamble or sync word).
Read back the AGC gain settings (AGC_GAIN_STATUS
register, Address 0x360).
Read the ADC_READBACK[7:0] bit values (Address
0x327 and Address 0x328; see the Analog-to-Digital
Converter section).
Re-enable the AGC by setting the AGC_MODE register
(Address 0x35D) = 0x00 (only necessary if AGC has not
already been locked on the preamble or sync word).
Calculate the RSSI in dBm as follows:
RSSI(dBm) =
where Gain_Correction is determined by the value of the
AGC_GAIN_STATUS register (Address 0x360) as shown
in Table 35.
⎛
⎜
⎝
1 ≈
7
ADC_READBA
1
8
⎛
⎜
⎝
1
+
1
8
+
64
1
CK[7:0]
⎞
⎟
⎠
GAIN_CORRECTION
44
35
26
17
10
0
×
1
7
+
Gain_Corre
ADF7023-J
ction
⎞
⎟
⎠
−
109