ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 97

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 137. 0x3FA: GPIO_CONFIGURE
Bit
[7:0]
Table 138. 0x3FD: TEST_DAC_GAIN
Bit
[7:4]
[3:0]
PACKET RAM REGISTER DESCRIPTION
Table 139. 0x00D: VAR_TX_MODE
VAR_TX_MODE
0
1
2
3
4 to 255
Name
GPIO_CONFIGURE
Name
Reserved
TEST_DAC_GAIN
R/W
R/W
R/W
R/W
R/W
Mode
Default; no transmit test mode
Reserved
Transmit the preamble continuously
Transmit the carrier continuously
Reserved
Reset
0
Reset
0
4
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Description
0x00: default
0x21: slicer output on GP5 (that is, bypass CDR)
0x40: limiter outputs on GP0(Q) and GP1(I)
0x41: filtered limiter outputs on GP0(Q) and GP1(I) and unfiltered limiter
outputs on GP2(Q) and IRQ_GP3 (I)
0x50: packet transmit data from communications processor on GP0
0x53: PA ramp finished on GP0
0xA0: Sport Mode 0
0xA1: Sport Mode 1
0xA2: Sport Mode 2
0xA3: Sport Mode 3
0xA4: Sport Mode 4
0xA5: Sport Mode 5
0xA6: Sport Mode 6
0xA7: Sport Mode 7
0xA8: Sport Mode 8
0xC9: Test DAC output on GP0 (also must set TEST_DAC_GAIN)
Description
Reserved
Set TEST_DAC_GAIN = 0 when using the test DAC
ADF7023-J