ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 40

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADF7023-J
Table 18. Sync Word Programming Examples
Required Sync Word (Binary,
First Bit Being First in Time)
000100100011010001010110
111010011100101000100
0001001000110100
011100001110
00010010
011100
1
Choice of Sync Word
The sync word should be chosen to have low correlation with the
preamble and have good autocorrelation properties. When the AFC
is set to lock on detection of sync word (AFC_LOCK_MODE = 3
and PREAMBLE_MATCH = 0), the sync word should be chosen
to be dc free, and it should have a run length limit not greater
than four bits.
PAYLOAD
The host processor writes the transmit data payload to the packet
RAM. The location of the transmit data in the packet RAM is
defined by the TX_BASE_ADR value register (Address 0x124).
The TX_BASE_ADR value is the location of the first byte of the
transmit payload data in the packet RAM. On reception of a
valid sync word, the communications processor automatically
loads the receive payload to the packet RAM. The RX_BASE_ADR
register value (Address 0x125) sets the location in the packet
RAM of the first byte of the received payload. For more details on
packet RAM memory, see the ADF7023-J Memory Map section.
Byte Orientation
The over-the-air arrangement of each transmitted packet RAM
byte can be set to MSB first or LSB first using the DATA_BYTE
setting in the PACKET_LENGTH_CONTROL register
(Address 0x126). The same orientation setting should be
used on the transmit and receive sides of the RF link.
Packet Length Modes
The ADF7023-J can be used in both fixed and variable length
packet systems. Fixed or variable length packet mode is set
using the PACKET_LEN variable setting in the PACKET_
LENGTH_CONTROL register (Address 0x126).
For a fixed packet length system, the length of the transmit and
received payload is set by the PACKET_LENGTH_MAX register
(Address 0x127). The payload length is defined as the number
of bytes from the end of the sync word to the start of the CRC.
In variable packet length mode, the communications processor
extracts the length field from the received payload data. In
transmit mode, the length field must be the first byte in the
transmit payload.
X = don’t care.
24
SYNC_WORD_
LENGTH Bits in
SYNC_CONTROL
Register (0x120)
21
16
12
8
6
SYNC_
BYTE_0
0x12
0x5D
0xXX
0xXX
0xXX
0xXX
1
Rev. 0 | Page 40 of 100
SYNC_
BYTE_1
0x34
0x39
0x12
0x57
0xXX
0xXX
1
The communications processor calculates the actual received
payload length as
where:
Length is the length field (the first byte in the received payload).
LENGTH_OFFSET is a programmable offset (set in the
PACKET_LENGTH_CONTROL register (Address 0x126).
The LENGTH_OFFSET value allows compatibility with
systems where the length field in the proprietary packet may
also include the length of the CRC and/or the sync word. The
ADF7023-J defines the payload length as the number of bytes
from the end of the sync word to the start of the CRC. In
variable packet length mode, the PACKET_LENGTH_MAX
value defines the maximum packet length that can be received,
as described in Figure 54.
VARIABLE
Addressing
The ADF7023-J provides a very flexible address matching scheme,
allowing matching of a single address, multiple addresses, and
broadcast addresses. The address information can be included
at any section of the transmit payload. The location of the
starting byte of the address data in the received payload is set in
the ADDRESS_MATCH_OFFSET register (Address 0x129), as
illustrated in Figure 55. The number of bytes in the first address
field is set in the ADDRESS_LENGTH register (Address 0x12A).
These settings allow the communications processor to extract the
address information from the received packet.
SYNC_
BYTE_2
0x56
0x44
0x34
0x0E
0x12
0x5C
Figure 54. Payload Length in Fixed and Variable Length Packet Modes
FIXED
RxPayload Length = Length + LENGTH_OFFSET − 4
PREAMBLE
PREAMBLE
Transmitted Sync Word (Binary,
First Bit Being First in Time)
0001_0010_0011_0100_0101_0110
0101_1101_0011_1001_0100_0100
0001_0010_0011_0100
0101_0111_0000_1110
0001_0010
0101_1100
RX PAYLOAD LENGTH = LENGTH + LENGTH_OFFSET – 4
WORD
WORD
SYNC
SYNC
TX PAYLOAD LENGTH = PACKET_LENGTH_MAX
RX PAYLOAD LENGTH = PACKET_LENGTH_MAX
LENGTH
TX PAYLOAD LENGTH = LENGTH
PAYLOAD
PAYLOAD
Receiver Sync
Word Match
Length (Bits)
24
21
16
12
8
6
CRC
CRC