ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 17

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 9. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Mnemonic
CREGRF1
RBIAS
CREGRF2
RFIO_1P
RFIO_1N
RFO2
VDDBAT2
NC
CREGVCO
VCOGUARD
CREGSYNTH
CWAKEUP
XOSC26P
XOSC26N
DGUARD
CREGDIG1
GP0
GP1
GP2
IRQ_GP3
Description
Regulator Voltage for RF. A 220 nF capacitor should be placed between this pin and ground for
regulator stability and noise rejection.
External Bias Resistor. A 36 kΩ resistor with 2% tolerance should be used.
Regulator Voltage for RF. A 220 nF capacitor should be placed between this pin and ground for
regulator stability and noise rejection.
LNA Positive Input in Receive Mode. PA positive output in transmit mode with differential PA.
LNA Negative Input in Receive Mode. PA negative output in transmit mode with differential PA.
Single-Ended PA Output.
Power Supply Pin Two. Decoupling capacitors to the ground plane should be placed as close as
possible to this pin.
No Connect.
Regulator Voltage for the VCO. A 220 nF capacitor should be placed between this pin and ground for
regulator stability and noise rejection.
Guard/Screen for VCO. This pin should be connected to Pin 9.
Regulator Voltage for the Synthesizer. A 220 nF capacitor should be placed between this pin and
ground for regulator stability and noise rejection.
External Capacitor for Wake-Up Control. A 150 nF capacitor should be placed between this pin and
ground.
The 26 MHz reference crystal should be connected between this pin and XOSC26N.
The 26 MHz reference crystal should be connected between this pin and XOSC26P.
Internal Guard/Screen for the Digital Circuitry. A 220 nF capacitor should be placed between this pin
and ground.
Regulator Voltage for Digital Section of the Chip. A 220 nF capacitor should be placed between this
pin and ground for regulator stability and noise rejection. This can be achieved by shorting it to
Pin 15 and sharing the capacitor to ground.
Digital GPIO Pin 0.
Digital GPIO Pin 1.
Digital GPIO Pin 2.
Interrupt Request, Digital GPIO Test Pin 3. An RC filter should be placed between this pin and the
host processor. Recommended values are R = 1.1 kΩ and C = 1.5 nF.
CREGRF1
CREGRF2
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. CONNECT EXPOSED PAD TO GND.
VDDBAT2
RFIO_1P
RFIO_1N
RBIAS
RFO2
NC
1
2
3
4
5
6
7
8
Figure 4. Pin Configuration
Rev. 0 | Page 17 of 100
ADF7023-J
(Not to Scale)
TOP VIEW
EPAD
24 CS
23 MOSI
22 SCLK
21 MISO
20 IRQ_GP3
19 GP2
18 GP1
17 GP0
ADF7023-J