ISL23328TFVZ-TK Intersil, ISL23328TFVZ-TK Datasheet - Page 14

• Manufacturer Part Number: ISL23328TFVZ-TK
• Description: IC DGTL POT 2CH 100K 14TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL23328TFVZ-TK

• Taps: 128
• Resistance (ohms): 100K
• Number Of Circuits: 2
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C (Device Address)
• Voltage - Supply: 1.2 V ~ 5.5 V, 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SERIAL CLOCK (SCL)
This input is the serial clock of the I
requires an external pull-up resistor, since a master is an open
drain output.
DEVICE ADDRESS (A2, A1, A0)
The address inputs are used to set the least significant 3 bits of
the 7-bit I
address serial data stream must match with the Address input
pins in order to initiate communication with the ISL23328. A
maximum of eight ISL23328 devices may occupy the I
bus (see Table 3).
V
Digital power source for the logic control section. It supplies an
internal level translator for 1.2V to 5.5V serial bus operation. Use
the same supply as the I
Principles of Operation
The ISL23328 is an integrated circuit incorporating two DCPs with
its associated registers and an I
communication between a host and the potentiometer. The resistor
array is comprised of individual resistors connected in series. At
either end of the array and between each resistor is an electronic
switch that transfers the potential at that point to the wiper.
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap positions.
Voltage at any DCP pins, RHi, RLi or RWi, should not exceed V
level at any conditions during power-up and normal operation.
The V
source. It should use the same supply as the I
which allows reliable communication with a wide range of
microcontrollers and is independent from the V
extremely important in systems where the master supply has
lower levels than DCP analog supply.
DCP Description
Each DCP is implemented with a combination of resistor elements
and CMOS switches. The physical ends of each DCP are equivalent
to the fixed terminals of a mechanical potentiometer (RHi and RLi
pins). The RWi pin of the DCP is connected to intermediate nodes,
and is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Register (WRi). When the WRi
of a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal
(RWi) is closest to its “Low” terminal (RLi). When the WRi register
of a DCP contains all ones (WRi[7:0] = 7Fh), its wiper terminal
(RWi) is closest to its “High” terminal (RHi). As the value of the WRi
increases from all zeroes (0) to all ones (127 decimal), the wiper
moves monotonically from the position closest to RLi to the
position closest to RHi. At the same time, the resistance between
RWi and RLi increases monotonically, while the resistance
between RHi and RWi decreases monotonically.
While the ISL23328 is being powered up, both WR0 and WR1
are reset to 40h (64 decimal), which positions RWi at the center
between RLi and RHi.
LOGIC
LOGIC
2
C interface slave address. A match in the slave
pin is the terminal for the logic control digital power
2
C logic source.
14
2
C serial interface providing direct
2
C serial interface. SCL
2
C logic source
CC
level. This is
2
C serial
ISL23328
CC
The WRi can be read or written to directly using the I
interface as described in the following sections.
Memory Description
The ISL23328 contains three volatile 8-bit registers: Wiper
Register WR0, Wiper Register WR1, and Access Control Register
(ACR). Memory map of the ISL23328 is shown in Table 1. The
Wiper Register WR0 at address 0, contains current wiper position
of DCP0; The Wiper Register WR1 at address 1 contains current
wiper position of DCP1. The Access Control Register (ACR) at
address 10h contains information and control bits described in
Table 2.
Shutdown Function
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, i.e., DCP is forced
to end-to-end open circuit and RW is connected to RL through a
2kΩ serial resistor as shown in Figure 25. Default value of the
SHDN bit is 1.
When the device enters shutdown, all current DCP WR settings are
maintained. When the device exits shutdown, the wipers will return
to the previous WR settings after a short settling time (see
Figure 26).
In shutdown mode, if there is a glitch on the power supply which
causes it to drop below 1.3V for more than 0.2 to 0.4µs, the
wipers will be RESET to their mid position. This is done to avoid
an undefined state at the wiper outputs.
NAME/
VALUE
ADDRESS
BIT #
(hex)
10
1
0
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
7
0
TABLE 2. ACCESS CONTROL REGISTER (ACR)
SHDN
6
REGISTER NAME
TABLE 1. MEMORY MAP
VOLATILE
WR1
WR0
5
0
ACR
2kΩ
4
0
3
0
RH
RW
RL
DEFAULT SETTING
2
0
(hex)
August 19, 2011
2
40
40
40
1
0
C serial
FN7902.0
0
0