ISL23448TFVZ-TK Intersil, ISL23448TFVZ-TK Datasheet - Page 15

• Manufacturer Part Number: ISL23448TFVZ-TK
• Description: IC DGTL POT 4CH 100K 20TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL23448TFVZ-TK

• Taps: 128
• Resistance (ohms): 100K
• Number Of Circuits: 4
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: 4-Wire SPI (Chip Select)
• Voltage - Supply: 1.2 V ~ 5.5 V, 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

When the device enters shutdown, all current DCP WR settings are
maintained. When the device exits shutdown, the wipers will return
to the previous WR settings after a short settling time (see
Figure 26).
In shutdown mode, if there is a glitch on the power supply which
causes it to drop below 1.3V for more than 0.2 to 0.4µs the
wipers will be RESET to their mid position. This is done to avoid
an undefined state at the wiper outputs.
SPI Serial Interface
The ISL23448 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with data
clocked in on the rising edge of SCK, and clocked out on the
falling edge of SCK. CS must be LOW during communication with
the ISL23448. The SCK and CS lines are controlled by the host or
master. The ISL23448 operates only as a slave device.
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
Where X means “do not care”.
0
I2
0
0
0
1
1
POWER-UP
SHDN ACTIVATED SHDN RELEASED
FIGURE 26. SHUTDOWN MODE WIPER RESPONSE
USER PROGRAMMED
I1
0
0
1
0
1
MID SCALE = 40H
I0
0
1
1
0
0
SHDN MODE
15
INSTRUCTION SET
TIME (s)
R4
R4
R4
X
X
X
AFTER SHDN
WIPER RESTORE TO
THE ORIGINAL POSITION
R3
R3
R3
X
X
X
TABLE 4. INSTRUCTION SET
R2
R2
R2
X
X
X
ISL23448
R1
R1
R1
X
X
X
Protocol Conventions
The SPI protocol contains Instruction Byte followed by one or more
Data Bytes. A valid Instruction Byte contains instruction as the three
MSBs, with the following five register address bits (see Table 3).
The next byte sent to the ISL23448 is the Data Byte.
Table 4 contains a valid instruction set for ISL23448.
If the [R4:R0] bits are zero, one, two or three then the read or write
is to the WRi register. If the [R4:R0] are 10000, then the operation
is to the ACR.
Write Operation
A write operation to the ISL23448 is a two or more bytes
operation. First, it requires that the CS transition from
HIGH-to-LOW. Then, the host sends a valid Instruction Byte,
followed by one or more Data Bytes to the SDI pin. The host
terminates the write operation by pulling the CS pin from
LOW-to-HIGH. Instruction is executed on the rising edge of CS
(see Figure 27).
Read Operation
A Read operation to the ISL23448 is a four byte operation. First,
it requires that the CS transition from HIGH-to-LOW. Then, the
host sends a valid Instruction Byte, followed by a “dummy” Data
Byte, NOP Instruction Byte and another “dummy” Data Byte to
the SDI pin. The SPI host receives the Instruction Byte (instruction
code + register address) and requested Data Byte from the SDO
pin on the rising edge of SCK during the third and fourth bytes,
respectively. The host terminates the read by pulling the CS pin
from LOW-to-HIGH (see Figure 28).
BIT #
R0
R0
R0
X
X
X
I2
7
TABLE 3. INSTRUCTION BYTE FORMAT
NOP
ACR READ
ACR WRTE
WRi or ACR READ
WRi or ACR WRTE
I1
6
I0
5
R4
4
OPERATION
R3
3
R2
2
August 19, 2011
R1
1
FN7905.0
R0
0