PIC18F1220-H/SS Microchip Technology, PIC18F1220-H/SS Datasheet - Page 128

• Manufacturer Part Number: PIC18F1220-H/SS
• Description: IC MCU 8BIT 4KB FLASH 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1220-H/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

current from destroying the bridge power switches. The
microcontroller instruction cycles (T
PIC18F1220/1320
15.5.6
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current (shoot-
through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from flow-
ing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
In the Half-Bridge Output mode, a digitally programmable
dead-band delay is available to avoid shoot-through
delay occurs at the signal transition from the non-active
state to the active state. See Figure 15-6 for an illustra-
tion. The lower seven bits of the PWM1CON register
(Register 15-2) sets the delay period in terms of
15.5.7
When the ECCP is programmed for any of the
Enhanced PWM modes, the active output pins may be
configured for auto-shutdown. Auto-shutdown immedi-
ately places the Enhanced PWM output pins into a
defined shutdown state when a shutdown event
occurs.
REGISTER 15-2:
DS39605F-page 126
bit 7
bit 6-0
PROGRAMMABLE DEAD-BAND
DELAY
ENHANCED PWM
AUTO-SHUTDOWN
PWM1CON: PWM CONFIGURATION REGISTER
bit 7
PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
PDC<6:0>: PWM Delay Count bits
Number of F
transition active and the actual time it transitions active.
Legend:
R = Readable bit
-n = Value at POR
PRSEN
R/W-0
goes away; the PWM restarts automatically
CY
OSC
or 4 T
R/W-0
PDC6
/4 (4 * T
OSC
).
OSC
R/W-0
PDC5
) cycles between the scheduled time when a PWM signal should
W = Writable bit
‘1’ = Bit is set
R/W-0
PDC4
A shutdown event can be caused by the INT0, INT1 or
INT2 pins (or any combination of these three sources).
The auto-shutdown feature can be disabled by not
selecting any auto-shutdown sources. The auto-
shutdown sources to be used are selected using the
ECCPAS2:ECCPAS0 bits (bits <6:4> of the ECCPAS
register).
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states, spec-
ified by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0
bits (ECCPAS<3:0>). Each pin pair (P1A/P1C and
P1B/P1D) may be set to drive high, drive low or be tri-
stated (not driving). The ECCPASE bit (ECCPAS<7>)
is also set to hold the Enhanced PWM outputs in their
shutdown states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
Note:
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PDC3
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
R/W-0
PDC2
© 2007 Microchip Technology Inc.
x = Bit is unknown
R/W-0
PDC1
R/W-0
PDC0
bit 0