PIC18F4680-H/ML Microchip Technology, PIC18F4680-H/ML Datasheet - Page 279
PIC18F4680-H/ML
Manufacturer Part Number
PIC18F4680-H/ML
Description
IC MCU 8BIT 64KB FLASH 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F4585-IPT.pdf
(482 pages)
Specifications of PIC18F4680-H/ML
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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REGISTER 23-2:
© 2007 Microchip Technology Inc.
bit 7-5
bit 4
bit 3-1
bit 0
bit 4-0
Mode 1, 2
Mode 0
CANSTAT: CAN STATUS REGISTER
OPMODE2:OPMODE0: Operation Mode Status bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Configuration mode
011 = Listen Only mode
010 = Loopback mode
001 = Disable/Sleep mode
000 = Normal mode
Mode 0:
Unimplemented: Read as ‘0’
ICODE3:ICODE1: Interrupt Code bits
When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This
code indicates the source of the interrupt. By copying ICODE3:ICODE1 to WIN2:WIN0 (Mode 0)
or EICODE4:EICODE0 to EWIN4:EWIN0 (Mode 1 and 2), it is possible to select the correct
buffer to map into the Access Bank area. See Example 23-2 for a code example. To simplify the
description, the following table lists all five bits.
Unimplemented: Read as ‘0’
Mode 1, 2:
EICODE4:EICODE0: Interrupt Code bits
See ICODE3:ICODE1 above.
OPMODE2
OPMODE2
bit 7
Legend:
R = Readable bit
-n = Value at POR
No interrupt
Error interrupt
TXB2 interrupt
TXB1 interrupt
TXB0 interrupt
RXB1 interrupt
RXB0 interrupt
Wake-up interrupt
RXB0 interrupt
RXB1 interrupt
RX/TX B0 interrupt
RX/TX B1 interrupt
RX/TX B2 interrupt
RX/TX B3 interrupt
RX/TX B4 interrupt
RX/TX B5 interrupt
Note 1: To achieve maximum power saving and/or able to wake-up on CAN bus activity,
R-1
R-1
2: If buffer is configured as receiver, EICODE bits will contain ‘10000’ upon interrupt.
(1)
(1)
switch CAN module in Disable mode before putting device to Sleep.
OPMODE1
OPMODE1
R-0
R-0
PIC18F2585/2680/4585/4680
(1)
(1)
W = Writable bit
‘1’ = Bit is set
Preliminary
OPMODE0
OPMODE0
Mode 0
00000
00010
00100
00110
01000
01010
01100
00010
-----
-----
-----
-----
-----
-----
-----
-----
R-0
R-0
(1)
(1)
EICODE4 EICODE3 EICODE2 EICODE1 EICODE0
R-0
R-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
ICODE3
Mode 1
00000
00010
00100
00110
01000
10001
10000
01110
10000
10001
10010
10011
10100
10101
10110
10111
R-0
R-0
ICODE2
R-0
R-0
x = Bit is unknown
ICODE1
DS39625C-page 277
R-0
R-0
00000
00010
00100
00110
01000
-----
10000
01110
10000
10000
10010
10011
10100
10101
10110
10111
Mode 2
(2)
(2)
(2)
(2)
(2)
U-0
R-0
—
bit 0
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