NUC140LD2CN Nuvoton Technology Corporation of America, NUC140LD2CN Datasheet - Page 281

• Manufacturer Part Number: NUC140LD2CN
• Description: IC MCU 32BIT 64KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC140LD2CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NuMicro™ NUC130/NUC140 Technical Reference Manual
Burst Mode
SPI controller can switch to burst mode by setting TX_NUM bit field (SPI_CNTRL[9:8]) to 0x01. In
burst mode, SPI can transmit/receive two transactions in one transfer. The SPI burst mode
waveform is showed below:
Figure 5-55 Two Transactions in One Transfer (Burst Mode)
LSB First
The LSB bit (SPI_CNTRL[10]) defines the data transmission either from LSB or MSB firstly to
start to transmit/receive data.
Transmit Edge
The TX_NEG bit (SPI_CNTRL[2]) defines the data transmitted out either at negative edge or at
positive edge of serial clock SPICLK.
Receive Edge
The Rx_NEG bit (SPI_CNTRL[1]) defines the data received in either at negative edge or at
positive edge of serial clock SPICLK.
Note: the settings of TX_NEG and RX_NEG are mutual exclusive. In other words, don’t transmit
and receive data at the same clock edge.
Word Suspend
These four bits field of SP_CYCLE (SPI_CNTRL[15:12]) provide a configurable suspend interval
2 ~ 17 serial clock periods between two successive transaction words in master mode. The
suspend interval is from the last falling clock edge of the preceding transaction word to the first
rising clock edge of the following transaction word if CLKP = 0. If CLKP = 1, the interval is from
the rising clock edge of the preceding transaction word to the falling clock edge of the following
transaction word. The default value of SP_CYCLE is 0x0 (2 serial clock cycles), but set these bits
field has no any effects on data transaction process if TX_NUM = 0x00.
Publication Release Date: June 14, 2011
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Revision V2.01