NUC140LD2CN Nuvoton Technology Corporation of America, NUC140LD2CN Datasheet - Page 295

• Manufacturer Part Number: NUC140LD2CN
• Description: IC MCU 32BIT 64KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC140LD2CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

[11]
[10]
NuMicro™ NUC130/NUC140 Technical Reference Manual
CLKP
LSB
Ex:
If the SPI clock rate equals system clock rate, that is to say, the DIV_ONE feature is
enabled, the burst mode suspend interval period is
In case of disabling the DIV_ONE feature, if SP_CYCLE = 2~15, suspend interval
period is
Ex:
if SP_CYCLE = 0, suspend interval period is
In case of enabling the DIV_ONE feature, if SP_CYCLE = 2~15, suspend interval
period is
Ex:
if SP_CYCLE = 0, suspend interval period is
Clock Polarity
1 = SPICLK idle high
0 = SPICLK idle low
LSB First
1 = The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from
For byte suspend interval and burst mode suspend interval:
For FIFO mode suspend interval: (SP_CYCLE can’t be set as 1)
(SP_CYCLE[3:0] + 2) * period of SPICLK + 1 system clock cycle
SP_CYCLE = 0x0 … 2 SPICLK clock cycle + 1 system clock cycle
SP_CYCLE = 0x1 … 3 SPICLK clock cycle + 1 system clock cycle
……
SP_CYCLE = 0xE … 16 SPICLK clock cycle + 1 system clock cycle
SP_CYCLE = 0xF … 17 SPICLK clock cycle + 1 system clock cycle
(SP_CYCLE[3:0] * 2 + 3.5) * period of system clock
(SP_CYCLE[3:0] + 3) * system clock cycle + 1 SPICLK clock cycle
SP_CYCLE = 0x2 … 5 system clock cycles + 1 SPICLK clock cycle
……
SP_CYCLE = 0xE … 17 system clock cycles + 1 SPICLK clock cycle
SP_CYCLE = 0xF … 18 system clock cycles + 1 SPICLK clock cycle
35 * system clock cycle + 1 SPICLK clock cycle
(SP_CYCLE[3:0] + 3.5) * system clock period
SP_CYCLE = 0x2 … 5.5 system clock periods
……
SP_CYCLE = 0xE … 17.5 system clock periods
SP_CYCLE = 0xF … 18.5 system clock periods
35.5 * system clock period
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Publication Release Date: June 14, 2011
Revision V2.01