R5F61668RD50FPV Renesas Electronics America, R5F61668RD50FPV Datasheet - Page 1100

• Manufacturer Part Number: R5F61668RD50FPV
• Description: MCU 3V 1024K I-TEMP 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RD50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 21 I
3. Restriction in transfer rate setting value in multi-master mode
4. Restriction in bit manipulation when the MST and TRS bits are set in multi-master mode
5. Notes on master receive mode
6. Setting of the module stop function
Rev. 2.00 Sep. 24, 2008 Page 1066 of 1468
REJ09B0412-0200
When the transfer rate of I
signal the width of which is unexpected may be output. To avoid this phenomenon, set a
transfer rate of 1/1.8 or more of the fastest rate of other master to the transfer rate of I
transfer rate. For example, if the fastest rate of other masters is 400 kbps, the I
of this LSI should be 223 kbps (= 400/1.8) or more.
When the MST and TRS bits are set to master slave mode by manipulating these bits
sequentially, the conflict state occurs as follows according to the timing that arbitration is lost;
The AL bit in ICSR is set to 0, and set to master mode (MST = 1, TRS = 1). There are the
following methods to avoid this phenomenon.
•
•
In master receive mode, the RDRF bit is set to 0 at the eighth rising clock, the SCL signal is
pulled to “Low” state. When ICDRR is read near at the eighth falling clock, the SCL signal
level is released and the ninth clock is outputted by fixing the eighth clock of receive data to
“Low” state. Reading ICDRR is not required. As a result, the failure to receive data occurs.
There are the following methods to avoid this phenomenon.
•
•
Operation of the IIC2 can be disabled or enabled using the module stop control register. The
initial setting is for operation of the IIC2 to be halted. Register access is enabled by clearing
module stop state. For details, see section 28, Power-Down Modes.
In multi-master mode, set the MST and TRS bits by MOV instruction.
When arbitration is lost, confirm that the MST and TRS bits are set to 0. If these bits are
set to other than 0, set these bits to 0.
In master receive mode, read ICDRR by the eighth rising clock.
In master receive mode, set the RCVD bit to 1 and process the bit by the communication
of every one byte.
2
C Bus Interface 2 (IIC2)
2
C transfer of this LSI is slower than that of other master, the SCL
2
C transfer rate
2
C