SAF-XC164CS-16F40FBB Infineon Technologies, SAF-XC164CS-16F40FBB Datasheet - Page 11
SAF-XC164CS-16F40FBB
Manufacturer Part Number
SAF-XC164CS-16F40FBB
Description
Manufacturer
Infineon Technologies
Datasheet
1.SAF-XC164CS-16F40FBB.pdf
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Table 2
Symbol Pin
RSTIN
P20.12
NMI
P0H.0-
P0H.3
Data Sheet
Num.
1
2
3
4 … 7 IO
Pin Definitions and Functions
Input
Outp.
I
IO
I
Function
Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the XC164CS.
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
Note: The reset duration must be sufficient to let the
For details, please refer to the description of P20.
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC164CS into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
For details, please refer to the description of PORT0.
hardware configuration signals settle.
External circuitry must guarantee low level at the
RSTIN pin at least until both power supply voltages
have reached the operating range.
9
General Device Information
Derivatives
V2.3, 2006-08
XC164CS
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