SAF-XC164CS-16F40FBB Infineon Technologies, SAF-XC164CS-16F40FBB Datasheet - Page 73
SAF-XC164CS-16F40FBB
Manufacturer Part Number
SAF-XC164CS-16F40FBB
Description
Manufacturer
Infineon Technologies
Datasheet
1.SAF-XC164CS-16F40FBB.pdf
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Table 22
Parameter
Output valid delay for:
RD, WR(L/H)
Output valid delay for:
BHE, ALE
Output valid delay for:
A23 … A16, A15 … A0 (on PORT1)
Output valid delay for:
A15 … A0 (on PORT0)
Output valid delay for:
CS
Output valid delay for:
D15 … D0 (write data, MUX-mode)
Output valid delay for:
D15 … D0 (write data, DEMUX-mode)
Output hold time for:
RD, WR(L/H)
Output hold time for:
BHE, ALE
Output hold time for:
A23 … A16, A15 … A0 (on PORT0)
Output hold time for:
CS
Output hold time for:
D15 … D0 (write data)
Input setup time for:
D15 … D0 (read data)
Input hold time
D15 … D0 (read data)
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
Note: The shaded parameters have been verified by characterization.
Data Sheet
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.
They are not subject to production test.
External Bus Cycle Timing (Operating Conditions apply)
1)
71
Symbol
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
tc
10
11
12
13
14
15
16
20
21
23
24
25
30
31
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
SR
SR
Min.
1
-1
1
3
1
3
3
-3
0
1
-3
1
24
-5
Limit Values
Electrical Parameters
Max.
13
7
16
16
14
17
17
3
8
13
3
13
–
–
Derivatives
V2.3, 2006-08
XC164CS
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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