AD8150AST Analog Devices Inc, AD8150AST Datasheet - Page 23

• Manufacturer Part Number: AD8150AST
• Description: IC CROSSPOINT SWIT 33X17 184LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD8150AST

• Rohs Status: RoHS non-compliant
• Function: Crosspoint Switch
• Circuit: 1 x 33:17
• Voltage Supply Source: Dual Supply
• Voltage - Supply, Single/dual (±): ±3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 184-LQFP
• Number Of Arrays: 1
• Differential Data Transmission: Yes
• Operating Supply Voltage (typ): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Cascading Capability: No
• Line Code: NRZ
• On-chip Buffers: Yes
• On-chip Mux/demux: No
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (typ): 3.3V
• Lead Free Status / RoHS Status: Not Compliant

CIRCUIT DESCRIPTION
The AD8150 is a high speed 33 × 17 differential crosspoint
switch designed for data rates up to 1.5 Gbps per channel. The
AD8150 supports PECL-compatible input and output levels
when operated from a 5 V supply (V
ECL-compatible levels when operated from a −5 V supply (V
= GND, V
a 3.3 V supply to interface with low voltage PECL circuits or a
−3.3 V supply to interface with low voltage ECL circuits. The
AD8150 utilizes differential current-mode outputs with
individual disable control, which facilitates busing together the
outputs of multiple AD8150s to assemble larger switch arrays.
This feature also reduces the system to assemble larger switch
arrays, reduces system crosstalk, and can greatly reduce power
dissipation in a large switch array. A single external resistor
programs the current for all enabled output stages, allowing for
user control over output levels with different output
termination schemes and transmission line characteristic
impedances.
HIGH SPEED DATA INPUTS (INxxP, INxxN)
The AD8150 has 33 pairs of differential voltage-mode inputs.
The common-mode input range extends from the positive
supply voltage (V
input levels (V
voltage is less than 300 mV. Unused inputs may be connected
directly to any level within the allowed common-mode input
range. A simplified schematic of the input circuit is shown in
Figure 32.
To maintain signal fidelity at the high data rates supported by
the AD8150, the input transmission lines should be terminated
as close to the input pins as possible. The preferred input
termination structure will depend primarily on the application
and the output circuit of the data source. Standard ECL
components have open emitter outputs that require pull-down
resistors. Three input termination networks suitable for this
type of source are shown in Figure 33. The characteristic
impedance of the transmission line is shown as Z
resistors, R1 and R2, in the Thevenin termination are chosen to
synthesize a V
open-circuit output voltage equal to V
EE
= −5 V). To save power, the AD8150 can run from
INxxP
TT
CC
source with an output resistance of Z
− 2 V). The minimum differential input
CC
Figure 32. Simplified Input Circuit
) down to include standard ECL or PECL
V
V
CC
EE
CC
CC
= 5 V, V
− 2 V. The load
INxxN
EE
O
= GND) or
. The
O
and an
Rev. A | Page 23 of 44
CC
resistors (R
to bias the emitter followers of the ECL source.
If the AD8150 is driven from a current-mode output stage such
as another AD8150, the input termination should be chosen to
accommodate that type of source, as explained in the following
section.
HIGH SPEED DATA OUTPUTS (OUTyyP, OUTyyN)
The AD8150 has 17 pairs of differential current-mode outputs.
The output circuit, shown in Figure 34, is an open-collector NPN
current switch with resistor-programmable tail current and output
compliance extending from the positive supply voltage (V
down to standard ECL or PECL output levels (V
outputs may be disabled individually to permit outputs from
multiple AD8150’s to be connected directly. Since the output
currents of multiple enabled output stages connected in this
way sum, care should be taken to ensure that the output
compliance limit is not exceeded at any time; this can be
achieved by disabling the active output driver before enabling
an inactive driver.
ECL SOURCE
Figure 33. AD8150 Input Termination from ECL/PECL Sources: a) Parallel
Termination Using V
V
CC
L
) in the differential termination scheme are needed
ECL SOURCE
Z
Z
O
O
V
(a)
Z
TT
O
V
= VCG2V
CC
TT
Supply; b) Thevenin Equivalent Termination; and
c) Differential Termination
Z
R
O
L
INxxN
INxxP
V
EE
R
(c)
L
ECL SOURCE
Z
Z
O
O
V
CC
2Z
O
Z O
Z O
(b)
INxxN
R2
INxxP
R1
V
CC
CC
V
EE
− 2 V). The
– 2V
AD8150
R2
R1
INxxN
INxxP
CC
)