AD8113JST Analog Devices Inc, AD8113JST Datasheet - Page 16

• Manufacturer Part Number: AD8113JST
• Description: IC VIDEO CROSSPOINT SWIT 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD8113JST

• Rohs Status: RoHS non-compliant
• Function: Video Crosspoint Switch
• Circuit: 1 x 16:16
• Voltage Supply Source: Dual Supply
• Voltage - Supply, Single/dual (±): ±4.5 V ~ 12.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Array Configuration: 16x16
• Number Of Arrays: 1
• Screening Level: Commercial
• Pin Count: 100
• Package Type: LQFP
• Power Supply Requirement: Triple
• Lead Free Status / RoHS Status: Not Compliant

AD8113
SHORT-CIRCUIT OUTPUT CONDITIONS
Although there is short-circuit current protection on the AD8113
outputs, the output current can reach values of 55 mA into a
grounded output. Any sustained operation with even one shorted
output will exceed the maximum die temperature and can result
in device failure (see Absolute Maximum Ratings).
APPLICATIONS
The AD8113 has two options for changing the programming of
the crosspoint matrix. In the first option a serial word of 80 bits
can be provided that will update the entire matrix each time.
The second option allows for changing a single output’s pro-
gramming via a parallel interface. The serial option requires
fewer signals, but more time (clock cycles) for changing the
programming, while the parallel programming technique requires
more signals, but can change a single output at a time and requires
fewer clock cycles to complete programming.
Serial Programming
The serial programming mode uses the device pins CE, CLK,
DATA IN, UPDATE, and SER/PAR. The first step is to assert a
LOW on SER/PAR in order to enable the serial programming
mode. CE for the chip must be LOW to allow data to be clocked
into the device. The CE signal can be used to address an indi-
vidual device when devices are connected in parallel.
The UPDATE signal should be high during the time that data is
shifted into the device’s serial port. Although the data will still
shift in when UPDATE is LOW, the transparent, asynchronous
latches will allow the shifting data to reach the matrix. This will
cause the matrix to try to update to every intermediate state as
defined by the shifting data.
The data at DATA IN is clocked in at every down edge of CLK.
A total of 80 bits must be shifted in to complete the program-
ming. For each of the 16 outputs, there are four bits (D0–D3)
that determine the source of its input followed by one bit (D4)
that determines the enabled state of the output. If D4 is LOW
(output disabled), the four associated bits (D0–D3) do not mat-
ter, because no input will be switched to that output.
The most-significant-output-address data is shifted in first, then
following in sequence until the least-significant-output-address
data is shifted in. At this point UPDATE can be taken low, which
will cause the programming of the device according to the data that
was just shifted in. The UPDATE registers are asynchronous and
when UPDATE is low (and CE is low), they are transparent.
If more than one AD8113 device is to be serially programmed in a
system, the DATA OUT signal from one device can be connected
to the DATA IN of the next device to form a serial chain. All of
the CLK, CE, UPDATE, and SER/PAR pins should be connected
in parallel and operated as described above. The serial data is input
to the DATA IN pin of the first device of the chain, and it will
ripple through to the last. Therefore, the data for the last device
in the chain should come at the beginning of the programming
sequence. The length of the programming sequence will be 80 bits
times the number of devices in the chain.
Parallel Programming
When using the parallel programming mode, it is not necessary to
reprogram the entire device when making changes to the matrix.
In fact, parallel programming allows the modification of a single
output at a time. Since this takes only one CLK/UPDATE
–16–
cycle, significant time savings can be realized by using parallel
programming.
One important consideration in using parallel programming is
that the RESET signal DOES NOT RESET ALL REGISTERS
in the AD8113. When taken LOW, the RESET signal will only
set each output to the disabled state. This is helpful during
power-up to ensure that two parallel outputs will not be active
at the same time.
After initial power-up, the internal registers in the device will
generally have random data, even though the RESET signal has
been asserted. If parallel programming is used to program one
output, then that output will be properly programmed, but the
rest of the device will have a random program state depending
on the internal register content at power-up. Therefore, when
using parallel programming, it is essential that ALL OUTPUTS
BE PROGRAMMED TO A DESIRED STATE AFTER
POWER-UP. This will ensure that the programming matrix is
always in a known state. From then on, parallel programming
can be used to modify a single output or more at a time.
In similar fashion, if both CE and UPDATE are taken LOW
after initial power-up, the random power-up data in the shift
register will be programmed into the matrix. Therefore, in order
to prevent the crosspoint from being programmed into an un-
known state, DO NOT APPLY LOW LOGIC LEVELS TO
BOTH CE AND UPDATE AFTER POWER IS INITIALLY
APPLIED. Programming the full shift register one time to a
desired state, by either serial or parallel programming after
initial power-up, will eliminate the possibility of programming
the matrix to an unknown state.
To change an output’s programming via parallel programming,
SER/PAR and UPDATE should be taken HIGH and CE should
be taken LOW. The CLK signal should be in the HIGH state.
The 4-bit address of the output to be programmed should be put
on A0–A3. The first four data bits (D0–D3) should contain the
information that identifies the input that gets programmed to the
output that is addressed. The fifth data bit (D4) will determine
the enabled state of the output. If D4 is LOW (output disabled),
then the data on D0–D3 does not matter.
After the desired address and data signals have been established,
they can be latched into the shift register by a high to low
transition of the CLK signal. The matrix will not be programmed,
however, until the UPDATE signal is taken low. It is thus pos-
sible to latch in new data for several or all of the outputs first via
successive negative transitions of CLK while UPDATE is held
HIGH, and then have all the new data take effect when UP-
DATE goes LOW. This is the technique that should be used
when programming the device for the first time after power-up
when using parallel programming.
POWER-ON RESET
When powering up the AD8113, it is usually desirable to have
the outputs come up in the disabled state. The RESET pin,
when taken LOW, will cause all outputs to be in the disabled
state. However, the RESET signal DOES NOT RESET ALL
REGISTERS in the AD8113. This is important when operating
in the parallel programming mode. Please refer to that section
for information about programming internal registers after
power-up. Serial programming will program the entire matrix
each time, so no special considerations apply.
REV. A