AT89C5131A-RDTIM Atmel, AT89C5131A-RDTIM Datasheet - Page 21

no-image

AT89C5131A-RDTIM

Manufacturer Part Number
AT89C5131A-RDTIM
Description
C5131A 32K FLASH USB VQFP64 IND, 5V
Manufacturer
Atmel
Datasheet
PLL Programming
Divider Values
4136C–USB–04/05
The PLL is programmed using the flow shown in Figure 9. As soon as clock generation
is enabled user must wait until the lock indicator is set to ensure the clock output is
stable.
Figure 9. PLL Programming Flow
To generate a 48 MHz clock using the PLL, the divider values have to be configured fol-
lowing the oscillator frequency. The typical divider values are shown in Table 27.
Table 27. Typical Divider Values
Oscillator Frequency
12 MHz
16 MHz
18 MHz
20 MHz
24 MHz
32 MHz
40 MHz
3 MHz
6 MHz
8 MHz
R+1
Configure Dividers
16
12
12
Programming
8
6
4
3
8
2
3
PLL Locked?
N3:0 = xxxxb
R3:0 = xxxxb
LOCK = 1?
Enable PLL
PLLEN = 1
PLL
N+1
10
1
1
1
1
1
3
5
1
2
AT89C5131
PLLDIV
F0h
B4h
B9h
70h
50h
30h
20h
72h
10h
21h
21

Related parts for AT89C5131A-RDTIM