AT89C51RD2-RDTIM Atmel, AT89C51RD2-RDTIM Datasheet - Page 53

• Manufacturer Part Number: AT89C51RD2-RDTIM
• Description: MCU 8-Bit AT89 80C51 CISC 64KB Flash 3.3V/5V 64-Pin VQFP Tray
• Manufacturer: Atmel

4235J–8051–01/08
Table 14-4.
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
FE/SM0
Number
7
Bit
7
6
5
4
3
2
1
0
SCON Register
SM1
6
Mnemonic
REN
SM0
SM1
SM2
TB8
RB8
Bit
FE
RI
TI
SM2
5
Description
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit.
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit.
Serial port Mode bit 1
SM0 SM1 Mode
0
0
1
1
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 14-2. and
Figure 14-3. in the other modes.
0
1
0
1
REN
Shift Register F
8-bit UART
9-bit UART
9-bit UART
4
Baud Rate
Variable
F
Variable
TB8
XTAL
XTAL
3
/12 (or F
/64 or F
AT89C51RD2/ED2
XTAL
XTAL
RB8
2
/32
/6 in mode X2)
TI
1
RI
0
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