STM32F407ZET6 STMicroelectronics, STM32F407ZET6 Datasheet - Page 19
![Microcontrollers (MCU) ARM M4 512 FLASH 168 Mhz 192kB SRAM](/photos/39/71/397107/lqfp-144_sml.jpg)
STM32F407ZET6
Manufacturer Part Number
STM32F407ZET6
Description
Microcontrollers (MCU) ARM M4 512 FLASH 168 Mhz 192kB SRAM
Manufacturer
STMicroelectronics
Datasheet
1.STM32F407ZGT6.pdf
(167 pages)
Specifications of STM32F407ZET6
Core
ARM Cortex M4
Processor Series
STM32F4
Data Bus Width
32 bit
Maximum Clock Frequency
168 MHz
Program Memory Size
512 KB
Data Ram Size
192 KB
On-chip Adc
Yes
Number Of Programmable I/os
114
Number Of Timers
10
Operating Supply Voltage
1.7 V to 3.6 V
Package / Case
LQFP-144
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
2
Interface Type
CAN, I2C, I2S, SPI, UART
Program Memory Type
Flash
Lead Free Status / Rohs Status
Details
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STM32F405xx, STM32F407xx
2.2.4
2.2.5
2.2.6
2.2.7
Embedded Flash memory
The STM32F40x devices embed a Flash memory of 256 Kbytes, 512 Kbytes, 768 Kbytes or
1 Mbytes available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
Embedded SRAM
All STM32F40x products embed:
●
●
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a
seamless and efficient operation even when several high-speed peripherals work
simultaneously.
Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)
data RAM
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or V
Doc ID 022152 Rev 2
BAT
mode.
Description
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