DS21372T+ Maxim Integrated Products, DS21372T+ Datasheet
DS21372T+
Specifications of DS21372T+
Related parts for DS21372T+
DS21372T+ Summary of contents
Page 1
FEATURES Generates/detects digital bit patterns for analyzing, evaluating and troubleshooting digital communications systems Operates at speeds from MHz Programmable polynomial length and feedback taps for generation of any other pseudorandom pattern bits in ...
Page 2
GENERAL OPERATION 1.1 PATTERN GENERATION The DS21372 is programmed to generate a particular test pattern by programming the following registers: - Pattern Set Registers (PSR) - Pattern Length Register (PLR) - Polynomial Tap Register (PTR) - Pattern Control Register ...
Page 3
POWER-UP SEQUENCE On power-up, the registers in the DS21372 will random state. The user must program all the internal registers to a known state before proper operation can be insured. DS21372 FUNCTIONAL BLOCK DIAGRAM Figure 1 ...
Page 4
DETAILED PIN DESCRIPTION Table 1 PIN SYMBOL TYPE DESCRIPTION AD0 I/O 3 AD1 I/O 4 TEST AD2 I/O 7 AD3 I/O 8 AD4 I/O 9 AD5 I/O 10 AD6 I/O ...
Page 5
PIN SYMBOL TYPE DESCRIPTION RDATA I 26 RDIS I 27 RCLK TCLK I 31 TDIS I 32 TDATA O DS21372 REGISTER MAP Table 2 ADDRESS R/W ...
Page 6
PARALLEL CONTROL INTERFACE The DS21372 is controlled via a multiplexed bi-directional address/data bus by an external microcontroller or microprocessor. The DS21372 can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel ...
Page 7
PLR: PATTERN LENGTH REGISTER (ADDRESS=04 HEX) (MSB SYMBOL POSITION - PLR1.7 - PLR1.6 - PLR1.5 LB4 PLR1.4 LB3 PLR1.3 LB2 PLR1.2 LB1 PLR1.1 LB0 PLR1.0 5. POLYNOMIAL TAP REGISTER Polynomial Tap Bits PT4 - PT0 determine the feedback ...
Page 8
PCR: PATTERN CONTROL REGISTER (ADDRESS=06 HEX) (MSB) TL QRSS SYMBOL POSITION TL PCR.7 QRSS PCR.6 PS PCR.5 LC PCR.4 RL PCR.3 SYNCE PCR.2 RESYNC PCR.1 LPBK PCR NAME AND DESCRIPTION Transmit Load. A low to high transition ...
Page 9
ERROR INSERT REGISTER The Error Insertion Register (EIR) controls circuitry within the DS21372 that allows the generated pattern to be intentionally corrupted. Bit errors can be inserted automatically at regular intervals by properly programming the EIR0 to EIR2 bits ...
Page 10
PSEUDORANDOM PATTERN GENERATION (PCR.5=1) Table 4 PATTERN TYPE Fractional T1 LB Activate ...
Page 11
REPETITIVE PATTERN GENERATION (PCR.5=0) Table 5 PATTERN TYPE all 1s all 0s alternating 1s and 0s double alternating 1s and Line Loopback Activate D4 Line Loopback ...
Page 12
BIT COUNT REGISTERS (MSB) BC31 BC30 BC29 BC23 BC22 BC21 BC15 BC14 BC13 BC7 BC6 BC5 9. BIT ERROR COUNT REGISTERS The Bit Error Count Registers (BECR3 to BECR0) comprise a 32-bit count of bits received in error at RDATA. ...
Page 13
PATTERN RECEIVE REGISTERS (MSB) PR31 PR30 PR29 PR23 PR22 PR21 PR15 PR14 PR13 PR7 PR6 PR5 11. STATUS REGISTER AND INTERRUPT MASK REGISTER The Status Register (SR) contains information on the current real time status of the DS21372. When a ...
Page 14
IMR: INTERRUPT MASK REGISTER (ADDRESS=15 HEX) (MSB) - RA1 SYMBOL POSITION - IMR.7 RA1 IMR.6 RA0 IMR.5 RLOS IMR.4 BED IMR.3 BCOF IMR.2 BECOF IMR.1 SYNC IMR.0 RA0 RLOS BED NAME AND DESCRIPTION Not Assigned. Should be set to 0 ...
Page 15
AC TIMING AND DC OPERATING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature for DS21372N Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these ...
Page 16
AC CHARACTERISTICS - PARALLEL PORT PARAMETER Cycle Time Pulse Width, DS Low or RD Pulse Width, DS High or RD Input Rise/Fall Times R/ Hold Times W R/ Setup Time Before DS High W Setup Time Before DS ...
Page 17
INTEL BUS READ AC TIMING (BTS=0) FIGURE 3 ALE PW t ASD WR t ASD AD0-AD7 t CYC ASH t ASED ASL DDR t AHL ...
Page 18
INTEL BUS WRITE AC TIMING (BTS=0) FIGURE 4 ALE PW t ASD RD t ASD AD0-AD7 t CYC ASH t ASED ASL t DSW t AHL ...
Page 19
MOTOROLA BUS AC TIMING (BTS=1) FIGURE ASD DS PW R/W AD0-AD7 (READ) CS AD0-AD7 (WRITE) ASH ASED EL t CYC t RWS t ASL t DDR t AHL ASL ...
Page 20
AC CHARACTERISTICS - RECEIVE SIDE PARAMETER RCLK Period RCLK Pulse Width RDATA Set Up to RCLK Rising RDATA Hold from RCLK Rising RDIS Set Up to RCLK Rising RDIS Hold from RCLK Rising RL and LC Pulse Width RCLK Rise ...
Page 21
RECEIVE AC TIMING Figure 6 TRANSMIT AC TIMING Figure 7 NOTE: When TDIS is high about the rising edge of TCLK, TDATA will not be updated and will be held with the previous valve until TDIS is low about the ...
Page 22
DS21372 32-PIN TQFP DIM MIN MAX A - 1.20 A1 0.05 0.15 A2 0.95 1.05 D 8.80 9.20 D1 7.00 BSC E 8.80 9.20 E1 7.00 BSC L 0.45 0.75 e 0.80 BSC B 0.30 0.45 C 0.09 0.20 22 ...