DS21372T+ Maxim Integrated Products, DS21372T+ Datasheet - Page 13

• Manufacturer Part Number: DS21372T+
• Description: IC TESTER BIT ERROR 3.3V 32-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21372T+

• Function: Bit Error Rate Tester (BERT)
• Interface: T1
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Includes: Error Counter, Pattern Generator and Detector
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

PATTERN RECEIVE REGISTERS
11. STATUS REGISTER AND INTERRUPT MASK REGISTER
The Status Register (SR) contains information on the current real time status of the DS21372. When a
particular event has occurred, the appropriate bit in the register will be set to a 1. All of the bits in these
registers (except for the SYNC bit) operate in a latched fashion. This means that if an event occurs and a
bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. For the BED, BCOF,
and BECOF status bits, they will be cleared when read and will not be set again until the event has
occurred again. For RLOS, RA0, and RA1 status bits, they will be cleared when read if the condition no
longer persists.
The SR register has the unique ability to initiate a hardware interrupt via the
and events in the SR can be either masked or unmasked from the interrupt pins via the Interrupt Mask
Register (IMR).
SR: STATUS REGISTER (ADDRESS=14 HEX)
(MSB)
PR31
PR23
PR15
(MSB)
PR7
SYMBOL
BECOF
-
BCOF
SYNC
RLOS
BED
RA1
RA0
-
PR30
PR22
PR14
PR6
RA1
PR29
PR21
PR13
POSITION
PR5
SR.7
SR.6
SR.5
SR.4
SR.3
SR.2
SR.1
SR.0
RA0
PR28
PR20
PR12
PR4
NAME AND DESCRIPTION
Not Assigned. Could be any value when read.
Receive All Ones. Set when 32 consecutive 1s are received;
allowed to be cleared when a 0 is received.
Receive All Zeros. Set when 32 consecutive 0s are received;
allowed to be cleared when a 1 is received.
Receive Loss Of Sync. Set when the device is searching for
synchronization. Once sync is achieved, will remain set until
read.
Bit Error Detection. Set when bit errors are detected.
Bit Counter Overflow. Set when the 32-bit BCR overflows.
Bit Error Count Overflow. Set when the 32-bit BECR
overflows.
Sync. Real time status of the synchronizer (this bit is not
latched). Will be set when synchronization is declared. Will be
cleared when 6 or more bits out of 64 are received in error (if
PCR.2 = 0).
RLOS
PR27
PR19
PR11
PR3
13 of 22
PR26
PR18
PR10
PR2
BED
PR25
PR17
PR9
PR1
BCOF
(LSB)
PR24
PR16
PR8
PR0
INT
BECOF
PRR3 (addr.=10 Hex)
PRR2 (addr.=11 Hex)
PRR1 (addr.=12 Hex)
PRR0 (addr.=13 Hex)
pin. Each of the alarms
SYNC
(LSB)
DS21372