DS2155LN+ Maxim Integrated Products, DS2155LN+ Datasheet - Page 22

• Manufacturer Part Number: DS2155LN+
• Description: IC TXRX T1/E1/J1 1-CHIP 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2155LN+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Signal Name:
Signal Description:
Signal Type:
A user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels.
Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the
receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in
applications where not all channels are used such as fractional service, 384kbps service, 768kbps, or ISDN–PRI.
Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and
for per-channel conditioning. See Section
Signal Name:
Signal Description:
Signal Type:
Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled.
Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RCLK wide, is output at this pin that identifies either frame (IOCR1.5 = 0) or multiframe
(IOCR1.5 = 1) boundaries. If set to output frame boundaries, then through IOCR1.6, RSYNC can also be set to
output double-wide pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin
can be enabled to be an input through IOCR1.4, at which a frame or multiframe boundary pulse is applied.
Signal Name:
Signal Description:
Signal Type:
An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries.
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled), is
output at this pin that identifies multiframe boundaries.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLK with the data out of the receive-side framer.
Signal Name:
Signal Description:
Signal Type:
1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the receive-side elastic store function is
enabled. Should be connected low in applications that do not use the receive-side elastic store. See Section
details on 4.096MHz and 8.192MHz operation using the IBO.
Signal Name:
Signal Description:
Signal Type:
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive-side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.
RCHBLK
Receive Channel Block
Output
RSER
Receive Serial Data
Output
RSYNC
Receive Sync
Input/Output
RFSYNC
Receive Frame Sync
Output
RMSYNC
Receive Multiframe Sync
Output
RDATA
Receive Data
Output
RSYSCLK
Receive System Clock
Input
RSIG
Receive Signaling Output
Output
18
for details.
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