DS2187S Maxim Integrated Products, DS2187S Datasheet - Page 2

• Manufacturer Part Number: DS2187S
• Description: IC RECEIVE LINE INTERFACE 20SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS2187S

• Function: Receive Line Interface
• Interface: T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 18mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: AMI / B8ZS / HDB3 Coded Signal Decoder
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

DS2187
DS2187 BLOCK DIAGRAM Figure 1
LINE INPUT
Input signals are coupled to the DS2187 via a 1:2 center-tapped transformer as shown in Figure 2. For T1
applications, R1 and R2 must be 200 ohms in order to properly terminate the line at 100 ohms. R1 and R2
are set at 150 or 240 ohms for CEPT applications. Special internal circuitry of the RTIP and RRING
inputs permits negative signal excursions below V
, which will occur in the circuit in Figure 2.
SS
PEAK DETECTOR AND SLICERS
Signal pulses present at RTIP and RRING are sampled by an internal peak detect circuit. The clock and
data slicer threshold are set for 50% of the sampled peak voltage.
Peak input levels at RRIP and RRING must exceed 0.6 volts to establish minimum slicer thresholds.
Signals below this level will cause RCL to transition high after 192 bit times.
CLOCK EXTRACTION
The DS2187 utilizes both frequency locked (FLL) and digital phase locked (DPLL) loops to recover data
and clock from the incoming AMI signal. T1 applications utilize a 18.528 MHz clock divided by either
11, 12, or 13 to match the phase of the incoming jittered line signal. This technique affords exceptional
jitter tracking which enables the DS2187 to meet the latest AT&T TR 62411 and ECSA jitter
specifications. A 24.576 MHz clock divided by 11, 12, or 13 provides jitter tracking in the CEPT mode.
The DPLL output is buffered and presented at RCLK. An on-chip, laser-trimmed, voltage-controlled
oscillator (V
) provides the precision 18.528 MHz and 24.576 MHz frequency sources utilized in the
CO
FLL. The FLL is a high-Q circuit which tracks the average frequency of the incoming signal, minimizing
the effect of the DPLL on output jitter.
During the acquisition time or if RCL goes high, the LOCK pin will go low to indicate a loss of
synchronization to the line signal. Once this pin goes high, the FLL has achieved frequency lock and
valid data is present at the RPOS and RNEG outputs.
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