SI3018-GS Silicon Laboratories Inc, SI3018-GS Datasheet - Page 51

• Manufacturer Part Number: SI3018-GS
• Description: IC VOICE DAA GCI/PCM/SPI 16SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3018-GS

• Function: Data Access Arrangement (DAA)
• Interface: Serial
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Includes: Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Register 3. Interrupt Mask
Reset settings = 0000_0000
Bit
Name
Type
7
6
5
4
3
2
1
0
Bit
LCSOM
DLCSM
DODM
ROVM
RDTM
BTDM
POLM
Name
FDTM
RDTM ROVM
R/W
D7
Ring Detect Mask.
0 = A ring signal does not cause an interrupt on the AOUT/INT pin.
1 = A ring signal causes an interrupt on the AOUT/INT pin.
Receive Overload Mask.
0 = A receive overload does not cause an interrupt on the AOUT/INT pin.
1 = A receive overload causes an interrupt on the AOUT/INT pin.
Frame Detect Mask.
0 = The communications link achieving frame lock does not cause an interrupt on the AOUT/
INT pin.
1 = The communications link achieving frame lock causes an interrupt on the AOUT/INT pin.
Billing Tone Detect Mask.
0 = A detected billing tone does not cause an interrupt on the AOUT/INT pin.
1 = A detected billing tone causes an interrupt on the AOUT/INT pin.
Drop Out Detect Mask.
0 = A line supply dropout does not cause an interrupt on the AOUT/INT pin.
1 = A line supply dropout causes an interrupt on the AOUT/INT pin.
Loop Current Sense Overload Mask.
0 = An interrupt does not occur when the LCS bits are all 1s.
1 = An interrupt occurs when the LCS bits are all 1s.
Delta Loop Current Sense Mask.
0 = An interrupt does not occur when the LCS bits change.
1 = An interrupt does occur when the LCS bits change.
Polarity Reversal Detect Mask.
Generated from bit 7 of the LVS register. When this bit transitions, it indicates that the polarity
of TIP and RING was switched.
0 = A polarity change on TIP and RING does not cause an interrupt on the AOUT/INT pin.
1 = A polarity change on TIP and RING causes an interrupt on the AOUT/INT pin.
R/W
D6
FDTM
R/W
D5
BTDM DODM LCSOM DLCSM
R/W
D4
R/W
D3
Rev. 1.05
R/W
D2
Function
R/W
D1
POLM
R/W
D0
Si3018/19/10
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