SI3018-F-GSR Silicon Laboratories Inc, SI3018-F-GSR Datasheet

Page 1

... The Voice DAA is available in one 20-pin TSSOP (Si3050) and one 16-pin TSSOP/SOIC (Si3018/19) and requires minimal external components. The Si3050 interfaces directly to standard telephony PCM interfaces. ...

Page 2

... Si3050 + Si3018/19 2 Rev. 1.31 ...

Page 3

... Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 5.28. Transhybrid Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.29. Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 5.30. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.31. Communication Interface Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.32. PCM Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.33. Companding in PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.34. 16 kHz Sampling Operation in PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.35. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.36. GCI Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Si3050 + Si3018/19 Rev. 1.31 Page 3 ...

Page 4

... Receive SC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.46. Transmit SC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Appendix—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7. Pin Descriptions: Si3050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 8. Pin Descriptions: Si3018/ 100 9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 11. Package Outline: 20-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13. Package Outline: 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Silicon Labs Si3050 Support Documentation ...

Page 5

... Notes: 1. The Si3050 specifications are guaranteed when the typical application circuit (including component tolerance) and any Si3050 and any Si3018/19 are used. See "2. Typical Application Schematic" on page 17 for the typical application circuit. 2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. ...

Page 6

... Si3050 + Si3018/19 Table 2. Loop Characteristics = = (V 3 °C for K-Grade, see Figure 1 on page Parameter Symbol DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage On-Hook Leakage Current Operating Loop Current Operating Loop Current DC Ring Current ...

Page 7

... Total Supply Current, Deep Sleep Notes not apply to C1A/C2A All inputs at 0 – 0.4 (CMOS levels). All inputs are held static except clock and all outputs unloaded D = (Static I 0 mA). OUT 3. RGDT is not functional in this state. Si3050 + Si3018/19 3 Symbol Test Condition – ...

Page 8

... Si3050 + Si3018/19 Table 4. AC Characteristics = = (V 3 °C for F/K-Grade Parameter Sample Rate PCLK Input Frequency Receive Frequency Response Receive Frequency Response 1 Transmit Full-Scale Level 1,3 Receive Full-Scale Level 4,5,6 Dynamic Range 4,5,6 Dynamic Range 4,5,6 Dynamic Range Transmit Total Harmonic ...

Page 9

... Note: Permanent device damage can occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods might affect device reliability. Si3050 + Si3018/ 8000 Hz, "2. Typical Application Schematic" on page 17 ...

Page 10

... Si3050 + Si3018/19 Table 6. Switching Characteristics—General Inputs = = (V 3 °C for K-Grade Parameter Cycle Time, PCLK PCLK Duty Cycle PCLK Jitter Tolerance Rise Time, PCLK Fall Time, PCLK 2 PCLK Before RESET  3 RESET Pulse Width CS, SCLK Before RESET Rise Time, Reset Notes: 1 ...

Page 11

... All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are = – 0 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform SCLK t su1 CS SDI t d1 SDO Si3050 + Si3018/ pF) L Test Symbol Conditions ...

Page 12

... Si3050 + Si3018/19 Table 8. Switching Characteristics—PCM Highway Serial Interface = = (V 3 °C for K-Grade Parameter Cycle Time PCLK Valid PCLK Inputs 2 FSYNC Period PCLK Duty Cycle PCLK Jitter-Tolerance FSYNC Jitter Tolerance Rise Time, PCLK Fall Time, PCLK Delay Time, PCLK Rise to DTX Active ...

Page 13

... FSYNC must be 8 kHz under all operating conditions. 3. Specification applies to PCLK fall to DTX tri-state when that mode is selected. PCLK t su1 FSYNC DRX t d1 DTX Figure 5. GCI Highway Interface Timing Diagram (1x PCLK Mode) Si3050 + Si3018/ pF) L Test Symbol Conditions ...

Page 14

... Si3050 + Si3018/19 PCLK FSYNC DRX DTX Figure 6. GCI Highway Interface Timing Diagram (2x PCLK Mode) Table 10. Digital FIR Filter Characteristics—Transmit and Receive = = (V 3.0 to 3.6 V, Sample Rate 8 kHz Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay Note: Typical FIR filter characteristics for Fs Table 11. Digital IIR Filter Characteristics— ...

Page 15

... Figure 8. FIR Receive Filter Passband Ripple For Figures 7–10, all filter plots apply to a sample rate kHz. For Figures 11–14, all filter plots apply to a sample rate kHz. Si3050 + Si3018/19 Figure 9. FIR Transmit Filter Response Figure 10. FIR Transmit Filter Passband Ripple Rev. 1.31 15 ...

Page 16

... Si3050 + Si3018/19 Figure 11. IIR Receive Filter Response Figure 12. IIR Receive Filter Passband Ripple Figure 13. IIR Transmit Filter Response 16 Figure 14. IIR Transmit Filter Passband Ripple Figure 15. IIR Receive Group Delay Figure 16. IIR Transmit Group Delay Rev. 1.31 ...

Page 17

... Typical Application Schematic Si3050 + Si3018/19 Rev. 1.31 17 ...

Page 18

... Si3050 + Si3018/19 3. Bill of Materials Component C1 C5, C6, C50, C51 C7 C8, C9 C10 1 C30, C31 2 D1, D2 Dual Diode, 225 mA, 300 V, (CMPD2004S) FB1, FB2 Q1 Q4, Q5 RV1 R5 R7 R10 R11 3 R12, R13 4 R15, R16 1 R30, R32 1 R31, R33 R51, R52, R53 Notes: 1. R7–R8 may be substituted for R30–R33 and C30–C31 for lower cost, but reduced CID performance. ...

Page 19

... The PWMM[1:0] bits (Register 1, bits 5:4) select one of three different PWM output modes for the AOUT signal, including a delta-sigma data stream kHz return to 0 PWM output, and a balanced 32 kHz PWM output. Si3050 + Si3018/19 R41 C41 ...

Page 20

... Si3050 + Si3018/19 5. Functional Description The Si3050 is an integrated direct access arrangement (DAA) providing a programmable line interface that meets global telephone line requirements. The Si3050 implements Silicon Laboratories’ patented isolation capacitor technology, which offers the highest level of integration by replacing an analog front end (AFE), an isolation transformer, relays, opto-isolators, and 4-wire hybrid with two highly-integrated ICs ...

Page 21

... See "5.16. DC Termination" on page 30 for DCV and MINI settings. 2. Supported for loop current  20 mA. 3. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom. Si3050 + Si3018/ ...

Page 22

... Si3050 + Si3018/19 Table 13. Country Specific Register Settings (Continued) Register 16 Country OHS Ireland 0 Israel 0 Italy 0 Japan 0 Jordan 0 Kazakhstan 0 Kuwait 0 Latvia 0 Lebanon 0 Luxembourg 0 Macao 0 2 Malaysia 0 Malta 0 Mexico 0 Morocco 0 Netherlands 0 New Zealand 0 Nigeria 0 Norway 0 Oman 0 Pakistan 0 Peru 0 Philippines 0 Poland 0 Portugal 0 Romania 0 Russia 0 Saudi Arabia ...

Page 23

... See "5.16. DC Termination" on page 30 for DCV and MINI settings. 2. Supported for loop current  20 mA. 3. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom. Si3050 + Si3018/ ...

Page 24

... The communications link is disabled by default. To enable it, the PDL bit (Register 6, bit 4) must be cleared. No communication between the Si3050 and Si3018/19 can occur until this bit is cleared. Allow the PLL to lock to the PCLK and FSYNC input signals before clearing the PDL bit. 5.5. Power Management The Si3050 supports four basic power management operation modes ...

Page 25

... DRX and DTX. Clearing the PDL bit disables this mode, and the DTX data switches to the receive data from the line side. When the PDL bit is cleared, the Si3050 + Si3018/19 FDT bit (Register 12, bit 6) becomes active to indicate that successful communication between the line side ...

Page 26

... DCV[1:0] bits. 5.12. Line Voltage/Loop Current Sensing The Si3050 can measure loop current with either the Si3018 or the Si3019 line-side device. The 5-bit LCS[4:0] register reports loop current measurements when off-hook. The Si3019 offers an additional register to report loop current to a finer resolution (LCS2[7:0]). ...

Page 27

... Figure 19. Typical Loop Current LCS Transfer Function (ILIM = 0) Si3050 + Si3018/19 register changes state. The edge-triggered interrupt is cleared by writing 0 to the POLI bit (Register 4, bit 0). The POLI bit is set each time bit 7 of the LVS register changes state, and must be written clear it ...

Page 28

... Si3050 + Si3018/19 5.12.2. Loop Current Measurement When the Si3050 is off-hook, the LCS[4:0] bits measure loop current in 3.3 mA/bit resolution. With the LCS[4:0] bits, a user can detect another phone going off-hook by monitoring the dc loop current. The line current sense transfer function is shown in Figure 19 and is detailed in Table 14 ...

Page 29

... RING (clear the RG bit, Register 32, bit 0). The CO detects this current flowing on RING and grounds TIP. This sets the TGD bit Si3050 + Si3018/19 (Register 32, bit 2). The DAA may then be taken off-hook and the relay in series with RING opened (clear the RG bit) ...

Page 30

... The Si3018 provides four ac termination impedances when used with the Si3050. The ACIM[3:0] bits in Register 30 are used to select the ac impedance setting on the Si3018. The four available settings for the Si3018 are listed in Table 16 ACIM[3:0] setting other than the four listed in Table 16 is selected, the ac termination 600  ...

Page 31

... Global complex impedance Si3050 + Si3018/19 5.18. Ring Detection for satisfying The ring signal is resistively coupled from TIP and RING The to the RNG1 and RNG2 pins. The Si3050 supports either full- or half-wave ring detection. With full-wave ring detection, the designer can detect a polarity reversal of the ring signal. See “ ...

Page 32

... Si3050 + Si3018/19 The RDT behavior is also based on the RNG1-RNG2 voltage. When the RFWE bit positive ring signal sets the RDT bit for a period of time. When the RFWE bit positive or negative ring signal sets the RDT bit. The RDT bit acts like a one shot. When a new ring signal is detected, the one shot is reset ...

Page 33

... Si3050 + Si3018/19 bits will be set. An external interrupt can optionally be triggered by the DODI bit by setting the DODM and INTE bits. 5.23. Billing Tone Filter (Optional) Optionally, a billing tone filter may be inserted between the line and the voice DAA to minimize disruptions caused by large billing tones. The notch filter design requires two notches, one at 12 kHz and one at 16 kHz ...

Page 34

... Type II CID. Do not continue CID data reception. Si3050 + Si3018/19 f. Set the OH bit to return to an off-hook state. Immediately after returning to an off-hook state, the off-hook counter must be allowed to expire. ...

Page 35

... The TGA3 and RGA3 bits select either gain or attenuation. The transmit and receive paths can be individually muted with the TXM and RXM bits (Register 15). The signal flow through the Si3050 and the Si3018/19 is shown in Figures 25–26. Rev. 1. ...

Page 36

... To Link Si3050 Figure 25. Si3018/19 Signal Flow Diagram DRX TXG3 TXG2 TXA3 1 dB 0.1 dB Gain Gain/ATT Steps Steps 1 dB 0.1 dB Attenuation Gain/ATT Steps Steps IIRE DTX RXG3 Digital RXA2 RXA3 Filter Figure 26. Si3050 Signal Flow Diagram 5.28. Transhybrid Balance The Si3050 contains an on-chip analog hybrid that performs the 2- to 4-wire conversion and near-end echo cancellation ...

Page 37

... Si3050 + Si3018/19 The PLL clock synthesizer settles quickly after powerup. However, the settling time depends on the PCLK frequency and it can be approximately predicted by the following equation 64/F settle PCLK For all valid PCLK frequencies listed above, the default line sample rate is 8 kHz. This sample rate can be increased to 16 kHz by setting the HSSM bit (Register 7, bit 3) ...

Page 38

... A value the PCM Transmit and Receive Start Count registers signifies that the MSB of the data should occur in the same cycle as the rising edge of FSYNC. Si3050 + Si3018/19 PCM Mode SPI Clock Input SPI Serial Data Input SPI Serial Data Output ...

Page 39

... Si3050 + Si3018/19 PCLK FSYNC PCLK_CNT DRX MSB DTX HI-Z MSB Figure 28. PCM Highway Transmission, Short FSYNC, Single Clock Cycle Delayed Transmission I Figure 29. PCM Highway Transmission, Long FSYNC (TXS = RXS = 0, PHCF = 0, TRI = LSB LSB (TXS = RXS = 0, PHCF = 0, TRI = Rev I-Z ...

Page 40

... FSYNC PCLK_CNT DRX DTX HI-Z Figure 30. PCM Highway Transmission, Long FSYNC, Delayed Data Transfer PCLK FSYNC PCLK_CNT DRX M SB DTX HI Figure 31. PCM Highway Double Clocked Transmission, Short FSYNC Si3050 + Si3018/ MSB MSB (TXS = RXS = 10, PHCF = 0, TRI = LSB LSB (TXS = RXS = 0, PHCF = 1, TRI = 1) Rev ...

Page 41

... Si3050 + Si3018/19 5.33. Companding in PCM Mode The Si3050 supports both µ-Law companding formats in addition to 16-bit linear data. The 8-bit companding schemes follow a segmented curve formatted as a sign bit, three chord bits, and four step bits. µ-Law is commonly used in North America and Japan, while A-Law is primarily used in Europe ...

Page 42

... Interval Size Number 256 128 __________________ Notes: 1. Characteristics are symmetrical about analog 0 with sign bit 2. Digital code includes inversion of both sign and magnitude bits. Si3050 + Si3018/19 Value at Segment Endpoints Digital Code 8159 10000000b . . . 4319 4063 10001111b . . . 2143 2015 10011111b . . . 1055 991 10101111b ...

Page 43

... Si3050 + Si3018/19 Table 22. A-Law Encode-Decode Characteristics Segment #Intervals x interval size Number 128 Notes: 1. Characteristics are symmetrical about analog 0 with sign bit 2. Digital code includes inversion of all even numbered bits. 44 Value at segment endpoints Digital Code 4096 3968 10101010b . . 2143 2015 10100101b . . . ...

Page 44

... Figure 35 broadcast to all devices connected to the chain is requested, the CID do not decrement. In this case, the same 8- or 16-bit data is presented to all channels regardless of the CID values. Si3050 + Si3018/19 duration of the 8-bit transfer (command/address or data), going high after the last rising edge of SCLK after the transfer ...

Page 45

... Si3050 + Si3018/19 SDO SCLK CPU CS SDI Figure 34. SPI Daisy Chain Control Architecture BRCT R SDI0 SDI1 SDI2 SDI3 SDI14 SDI15 Figure 35. Sample SPI Control Byte to Access Channel 0 46 SCLK SDI CS Channel 0 SDO SDITHRU SDI SCLK CS Channel 1 SDO SDITHRU SCLK SDI CS Channel 15 SDO ...

Page 46

... SCLK after the DATA byte to indicate to the state machine that only one byte should be transferred. The state of the SDI pin is ignored during the DATA byte of a read operation CLK S DI CONTROL S DO Figure 39. Write Operation via a 16-bit SPI Port Si3050 + Si3018/ DDRE S S ADDRESS A DDRE S S Data [7:0] Rev ...

Page 47

... Si3050 + Si3018/ CLK S DI CONTROL S DO Figure 40. Read Operation via a 16-bit SPI Port Figures 39 and 40 illustrate WRITE and READ operations via a 16-bit SPI controller. These operations require a 4-byte transfer arranged as two 16-bit words. The CS pin does not go high when the eighth bit of data ...

Page 48

... B1 0 Channel Figure 41. Time-Multiplexed GCI Highway Frame Structure Si3050 + Si3018/19 used with a 16 kHz sample rate, the samples are transmitted in both the B1 and B2 channels of a single subframe. If 16-bit linear mode is used, the resulting 16-bit samples are transmitted in both the B1 and B2 channels of two consecutive subframes. In this case, assign one DAA per two subframes ...

Page 49

... Si3050 + Si3018/19 1st Byte MX Transm itter MX MR Receiver MR 1st Byte Figure 42. Monitor Handshake Timing The Idle state is achieved by the MX and MR bits being held inactive (signal is high) for two or more frames. When a transmission is initiated by a host device, an active state (signal is low) is present on the downstream MX bit ...

Page 50

... If an EOM is detected before a valid command sequence is communicated, the Si3050 returns to the idle state and remains unchanged. Si3050 + Si3018/19 The data presented to the Si3050 in the downstream Monitor bits must be present for two consecutive frames to be considered valid data. The Si3050 checks to ensure it receives the same data in two consecutive frames ...

Page 51

... Si3050 + Si3018/19 Idle 1st Byte Received Byte Valid New Byte Figure 43. Si3050 Monitor Receiver State Diagram 52 Initial State MX Abort ABT MX Any State nth Byte received MR: MR bit calculated and transmitted on DTX line. MX: MX bit received data downstream (DRX line). LL: Last look of monitor byte received on DRX line. ...

Page 52

... MX: MX bit calculated and expected on DTX line. MXR: MX bit s am pled on DTX line. CLS: Collis ion within the m onitor data byte on DTX line. RQT: Reques t for trans ion from internal s ource. ABT: Abort reques t/indication. Figure 44. Si3050 Monitor Transmitter State Diagram Si3050 + Si3018/19 MXR Abort MR x MXR ...

Page 53

... Si3050 + Si3018/19 54 Rev. 1.31 ...

Page 54

... Si3050 + Si3018/19 Rev. 1.31 55 ...

Page 55

... Si3050 + Si3018/19 5.40. Summary of Monitor Channel Com- mands Communication with the Si3050 should be in the following format: Byte 1: Device Address Byte Byte 2: Command Byte Byte 3: Register Address Byte Bytes 4-n: Data Bytes Bytes n+1, n+2: EOM 5.41. Device Address Byte The Device Address byte identifies which device connected to the GCI highway receives the particular message ...

Page 56

... SC channel just stored not match the C/I bits stored in S, but DO match the C/I bits stored in P, then the single set of C/I bits stored in the S latch are invalidated, and the current state of the C/I bits in P remains unchanged. Si3050 + Si3018/ CIR3 CIR2 C/I Bits Rev ...

Page 57

... Si3050 + Si3018/19 Receive New CI Code = P? No Store in S Receive New C/I Code = Figure 47. Protocol for Receiving C/I Bits in the Si3050 5.46. Transmit SC Channel The following diagram shows the definition of the transmitted SC channel, which is transmitted MSB first. MSB CIT6 CIT5 CIT4 These bits are defined as follows: ...

Page 58

... Line Current/Voltage Threshold Interrupt 44 Line Current/Voltage Threshold Interrupt Control 45–52 Programmable Hybrid Register 1–8 53–58 Reserved 59 Spark Quenching Control *Note: Bit is available for Si3019 line-side device only. Si3050 + Si3018/19 Table 24. Register Summary Bit 7 Bit 6 Bit 5 Bit 4 SR PWMM[1:0] INTE INTP WDTEN ...

Page 59

... Si3050 + Si3018/19 Register 1. Control 1 Bit D7 D6 Name SR Type R/W Reset settings = 0000_0000 Bit Name 7 SR Software Reset Enables the DAA for normal operation Sets all registers to their reset value. Note: Bit automatically clears after being set. 6 Reserved Read returns zero. 5:4 PWMM[1:0] Pulse Width Modulation Mode ...

Page 60

... RDTI bit) before the end of the ring burst in order for both interrupts to occur. 1 HBE Hybrid Enable Disconnects hybrid in transmit path Connects hybrid in transmit path. 0 RXE Receive Enable Receive path disabled Enables receive path. Si3050 + Si3018/ WDTEN R/W Function Rev. 1. RDI ...

Page 61

... Si3050 + Si3018/19 Register 3. Interrupt Mask Bit D7 D6 Name RDTM ROVM Type R/W R/W Reset settings = 0000_0000 Bit Name 7 RDTM Ring Detect Mask ring signal does not cause an interrupt on the AOUT/INT pin ring signal causes an interrupt on the AOUT/INT pin. 6 ROVM Receive Overload Mask. ...

Page 62

... AOUT/INT pin. This bit must be written clear it. Note: LCSOI does not necessarily imply that an overcurrent situation has occurred. An overcurrent situation in the DAA is determined by the status of the OPD bit (Register 19). After the LCSOI interrupt fires, the OPD bit should be checked to determine if an overcurrent situation exists. Si3050 + Si3018/ ...

Page 63

... Si3050 + Si3018/19 Bit Name 1 TGDI TIP Ground Detect Interrupt. This bit is reverse logic as compared to the TGD bit The CO has not grounded TIP causing current to flow The CO has grounded TIP, causing current to flow. Once set, this bit must be written clear it. If the TDGM bit (Register 3) and INTE bit (Register 3) are set, a hardware interrupt occurs on the AOUT/INT pin ...

Page 64

... Only a positive ring sets this bit when RFWE = 0. When RFWE = 1, either a positive or negative ring sets this bit Indicates a ring is occurring. 1 Reserved Read returns zero Off-Hook Line-side device on-hook Causes the line-side device to go off-hook. Si3050 + Si3018/ RDTP ONHM R R/W Function Rev. 1.31 ...

Page 65

... Si3050 + Si3018/19 Register 6. DAA Control 2 Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4 PDL Powerdown Line-Side Device Normal operation. Program the clock generator before clearing this bit Places the line-side device in lower power mode. 3 PDN Powerdown System-Side Device ...

Page 66

... Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. Digital Data Loopback. 0 DDL 0 = Normal operation Takes data received on DRX and loops it back out to DTX before the TX and RX filters. Output data is identical to the input data. Si3050 + Si3018/ Function Function Rev. 1. ...

Page 67

... Si3050 + Si3018/19 Register 11. System-Side and Line-Side Device Revision Bit D7 D6 Name LSID[3:0] Type Reset settings = xxxx_xxxx Bit Name 7:4 LSID[3:0] Line-Side ID Bits. These four bits will always read one of the following values, depending on which line-side device is used: Device Si3018 Si3019 3:0 REVA[3:0] System-Side Revision ...

Page 68

... Register 14. DAA Control 4 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1 RPOL Ring Detect Polarity The RGDT pin is active low The RGDT pin is active high. 0 Reserved Read returns zero. Si3050 + Si3018/ REVB[3:0] R Function Function Rev. 1. RPOL R/W ...

Page 69

... Si3050 + Si3018/19 Register 15. TX/RX Gain Control 1 Bit D7 D6 Name TXM Type R/W Reset settings = 0000_0000 Bit Name 7 TXM Transmit Mute Transmit signal is not muted Mutes the transmit signal. 6:4 Reserved Read returns zero. 3 RXM Receive Mute Receive signal is not muted Mutes the receive signal. ...

Page 70

... This bit, in combination with the RT2 bit, is used to satisfy country requirements on ring detec- tion. Signals below the lower level do not generate a ring detection; signals above the upper level are guaranteed to generate a ring detection. RT RT2 Si3050 + Si3018/ IIRE R/W Function SQ[1:0] Mean On-Hook Speed 00 Less than 0 ±10% (meets ETSI standard ± ...

Page 71

... Si3050 + Si3018/19 Register 17. International Control 2 Bit D7 D6 Name CALZ MCAL Type R/W R/W Reset settings = 0000_0000 Bit Name 7 CALZ Clear ADC Calibration Normal operation Clears the existing ADC calibration data. This bit must be written back to 0 after being set. 6 MCAL Manual ADC Calibration. ...

Page 72

... RNGV RFWE Reserved Read returns zero. Si3050 + Si3018/19 Function Function RGDT Half-Wave Full-Wave Validated Ring Envelope Ring Threshold Crossing One-Shot Rev. 1. ...

Page 73

... Si3050 + Si3018/19 Register 19. International Control 4 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 OVL Receive Overload Detect. This bit has the same function as ROV (Register 17), but clears itself after the overload is removed. See “5.22.Receive Overload Detection” on page 33. This bit is only masked by the off-hook counter and is not affected by the BTE bit ...

Page 74

... When decremented from the default settings, these bits linearly attenuate the AOUT trans- mit path signal used for call progress monitoring. Setting the bits to all 0s mutes the AOUT transmit path. Attenuation = 20 log(ATM[7:0]/64) 1111_1111 = +12 dB (gain) 0111_1111 = +6 dB (gain) 0100_0000 = 0 dB 0010_0000 = –6 dB (attenuation) 0001_0000 = –12 dB ... 0000_0000 = Mute Si3050 + Si3018/ ARM[7:0] R/W Function ATM[7:0] ...

Page 75

... Si3050 + Si3018/19 Register 22. Ring Validation Control 1 Bit D7 D6 Name RDLY[1:0] Type R/W Reset settings = 1001_0110 Bit Name Ring Delay Bits 1 and 0. 7:6 RDLY[1:0] These bits, in combination with the RDLY[2] bit (Register 23), set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. ...

Page 76

... These bits set the amount of time that the ring frequency must be within the tolerances set by the RAS[5:0] bits and the RMX[5:0] bits to be classified as a valid ring signal. RCC[2:0] 000 001 010 011 100 101 110 111 Si3050 + Si3018/ RTO[3:0] R/W Function RDLY[1:0] Delay 00 0 ...

Page 77

... Si3050 + Si3018/19 Register 24. Ring Validation Control 3 Bit D7 D6 Name RNGV Type R/W Reset settings = 0001_1001 Bit Name 7 RNGV Ring Validation Enable Ring validation feature is disabled Ring validation feature is enabled in both normal operating mode and low-power mode. 6 Reserved This bit must always be written to 0. ...

Page 78

... Current limiting mode disabled Current limiting mode enabled. This mode limits loop current to a maximum per the TBR21 standard. DC Impedance Selection. 0 DCR  dc termination is selected. This mode should be used for all standard applications 800  dc termination is selected. Si3050 + Si3018/ MINI[1:0] 0 R/W Function 3 ...

Page 79

... Si3050 + Si3018/19 Register 27. Reserved Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not write to these register bits. Register 28. Loop Current Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 LCS2[7:0] Loop Current Status. Eight-bit value returning the loop current. Each bit represents 1 loop current. ...

Page 80

... Global impedance Si3050 + Si3018/ FULL2 R/W Function Rev. 1.31 ...

Page 81

... Si3050 + Si3018/19 Register 31. DAA Control 5 Bit D7 D6 Name FULL FOH[1:0] Type R/W Reset settings = 0010_0000 Bit Name 7 FULL Full Scale Transmit and Receive Mode Default Transmit/receive full scale. This bit changes the full scale of the ADC and DAC from 0 dBm min to +3.2 dBm into a 600  ...

Page 82

... The external relay connecting TIP to an isolated supply is open. In this state, the DAA is unable to determine if the CO has grounded TIP Ring Ground The external relay connecting RING to ground is closed, causing current to flow in RING The external relay connecting RING to ground is open, not allowing current to flow in RING. Si3050 + Si3018/ Function Rev. 1. ...

Page 83

... Si3050 + Si3018/19 Register 33. PCM/SPI Mode Select Bit D7 D6 Name PCML Type R/W R/W Reset settings = 0000_0000 Bit Name PCM Analog Loopback. 7 PCML 0 = Normal operation Enables analog data to be received from the line, converted to digital data and trans- mitted across the ISOcap link. The data passes through the RX filter and is looped back through the TX filter and is transmitted back out to the line ...

Page 84

... Register 36. PCM Receive Start Count—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RXS[7:0] PCM Receive Start Count. PCM Receive Start Count equals the number of PCLKs following FSYNC before data reception begins. Si3050 + Si3018/ TXS[7:0] R/W Function Function ...

Page 85

... Si3050 + Si3018/19 Register 37. PCM Receive Start Count—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 RXS[1:0] PCM Receive Start Count. PCM Receive Start Count equals the number of PCLKs following FSYNC before data reception begins ...

Page 86

... RGA2 RXG2[3:0] X 0000 0 0001 0 0 11xx 1 0001 1 1 1111 Si3050 + Si3018/ RGA2 R/W Function Result 0 dB gain or attenuation is applied to the receive path gain is applied to the receive path gain is applied to the receive path attenuation is applied to the receive path attenuation is applied to the receive path. ...

Page 87

... Si3050 + Si3018/19 Register 40. TX Gain Control 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 TGA3 Transmit Gain or Attenuation Incrementing the TGA3[3:0] bits results in gaining up the transmit path Incrementing the TGA3[3:0] bits results in attenuating the transmit path. ...

Page 88

... Incrementing the RXG3[3:0] bits results in attenuating the receive path. 3:0 RXG3[3:0] Receive Gain 3. Each bit increment represents 0 gain or attenuation maximum of 1.5 dB. For example: RGA3 RXG3[3: Si3050 + Si3018/ RGA3 R/W Function Result 0000 0 dB gain or attenuation is applied to the receive path. 0001 0.1 dB gain is applied to the receive path. : 1111 1 ...

Page 89

... Si3050 + Si3018/19 Register 42. GCI Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3:2 GCIF[1:0] GCI Data Format A-Law µ-Law 8-bit linear. The top 8-bits of the 16-bit linear signal are transferred, and the bottom 8-bits are discarded ...

Page 90

... The current/voltage threshold is triggered by the absolute value of the number in either the LCS2 or LVS register falling below the value in the CVT[7:0] register The current/voltage threshold is triggered by the absolute value of the number in either the LCS2 or LVS register rising above the value in the CVT[7:0] register. Si3050 + Si3018/ ...

Page 91

... Si3050 + Si3018/19 Register 45. Programmable Hybrid Register 1 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB1[7:0] Programmable Hybrid Register 1. These bits can be programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the first tap in the eight-tap filter. When this register is set to all 0s, this filter stage does not have an effect on the hybrid response. See the section entitled " ...

Page 92

... This register represents the fourth tap in the eight-tap filter. When this register is set to all 0s, this filter stage does not have an effect on the hybrid response. See the section entitled "5.28. Transhybrid Balance" on page 37 for more information on selecting coefficients for the programmable hybrid. Si3050 + Si3018/ ...

Page 93

... Si3050 + Si3018/19 Register 49. Programmable Hybrid Register 5 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB5[7:0] Programmable Hybrid Register 5. These bits can be programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the fifth tap in the eight-tap filter. When this register is set to all 0s, this filter stage does not have an effect on the hybrid response. See the section entitled " ...

Page 94

... Transhybrid Balance" on page 37 for more information on selecting coefficients for the programmable hybrid. Register 53-58. Reserved Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not write to these register bits. Si3050 + Si3018/ HYB7[7:0] R/W Function HYB8[7:0] R/W Function ...

Page 95

... Si3050 + Si3018/19 Register 59. Spark Quenching Control Bit D7 D6 Name SQ1 Type R/W Reset settings = xxxx_xxxx Bit Name 7 Reserved Always write this bit to zero. Spark Quenching. 6 SQ1 This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets the amount of time for the line-side device to go on-hook. The on-hook speeds specified are measured from the time the OH bit is cleared until loop current equals zero ...

Page 96

... A —UL1950 3 PPENDIX RD Introduction Although designs using the Si3018 and Si3019 comply with UL1950 3rd Edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. Figure 48 shows two designs that can pass the UL1950 overvoltage tests and electromagnetic emissions. The ...

Page 97

... Si3050 + Si3018/19 7. Pin Descriptions: Si3050 AOUT/INT Pin # Pin Name 1 SDO Serial Port Data Output. Serial port control data output. 2 SDI Serial Port Data Input. Serial port control data input Chip Select Input. An active low input control signal that enables the SPI Serial port. When inactive, SCLK and SDI are ignored and SDO is high impedance ...

Page 98

... Connects to the system digital ground. 19 SCLK Serial Port Bit Clock Input. Controls the serial data on SDO and latches the data on SDI. 20 SDITHRU SDI Passthrough Output. Cascaded SDI output signal to daisy-chain the SPI interface with additional devices. Si3050 + Si3018/19 Description Rev. 1.31 99 ...

Page 99

... Si3050 + Si3018/19 8. Pin Descriptions: Si3018/19 Pin # Pin Name 1 QE Transistor Emitter. Connects to the emitter of Q3. 2 DCT DC Termination. Provides dc termination to the telephone network Receive Input. Serves as the receive side input from the telephone network Internal Bias. Provides a bias voltage to the device. 5 C1B Isolation Capacitor 1B ...

Page 100

... Pin # Pin Name 14 DCT3 DC Termination 3. Provides dc termination to the telephone network. 15 IGND Isolated Ground. Connects to ground on the line-side interface. 16 DCT2 DC Termination 2. Provides dc termination to the telephone network. Si3050 + Si3018/19 Description Rev. 1.31 101 ...

Page 101

... Si3050 + Si3018/19 9. Ordering Guide System-side Chipset Region (TSSOP) Si3050 + Enhanced Global Si3050-E-FT Si3019-F-FS Si3019-F-FT Si3019 Si3050 + Enhanced Global Si3050-E-GT Si3019-F-GS Si3019-F-GT Si3019 Si3050 + Global Si3050-E-FT Si3018-F-FS Si3018-F-FT Si3018 Note: Refer to "10. Product Identification" on page 102 for more information on part naming conventions. ...

Page 102

... Package Outline: 20-Pin TSSOP Figure 49 illustrates the package details for the Si3050. Table 26 lists the values for the dimensions shown in the illustration. Figure 49. 20-Pin Thin Shrink Small Outline Package (TSSOP) Si3050 + Si3018/19 Rev. 1.31 103 ...

Page 103

... Si3050 + Si3018/19 Table 26. 20-Pin TSSOP Package Diagram Dimensions Dimension θ aaa bbb ccc Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components ...

Page 104

... Package Outline: 16-Pin SOIC Figure 50 illustrates the package details for the Si3018/19. Table 27 lists the values for the dimensions shown in the illustration. Figure 50. 16-Pin Small Outline Integrated Circuit (SOIC) Package Si3050 + Si3018/19 Rev. 1.31 105 ...

Page 105

... Si3050 + Si3018/19 Table 27. 16-Pin SOIC Package Diagram Dimensions Dimension θ aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components ...

Page 106

... Package Outline: 16-Pin TSSOP Figure 51 illustrates the package details for the Si3018/19. Table 28 lists the values for the dimensions shown in the illustration. Figure 51. 16-Pin Thin Shrink Small Outline Package (TSSOP) Si3050 + Si3018/19 Rev. 1.31 107 ...

Page 107

... Si3050 + Si3018/19 Table 28. 16-Pin TSSOP Package Diagram Dimensions Dimension θ aaa bbb ccc Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AB. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components ...

Page 108

... AN77: Silicon DAA Software Guidelines (Si3050)  AN81: Emissions Design Considerations  AN84: Digital Hybrid with the Si305x DAAs  Si3050PPT-EVB Data Sheet  Note: Refer to www.silabs.com for a current list of support documents for this chipset. Si3050 + Si3018/19 D UPPORT OCUMENTATION Rev. 1.31 109 ...

Page 109

... Corrected ACIM settings for Brazil.  Updated "5.3. Initialization" on page 24.  Revised Step 6 with standard hexadecimal notation.  Updated Figure 25, “Si3018/19 Signal Flow  Diagram,” on page 37. Corrected HPF pole.  Updated "9. Ordering Guide" on page 102.  ...

Page 110

... N : OTES Si3050 + Si3018/19 Rev. 1.31 111 ...

Page 111

... Si3050 + Si3018/ ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: SiDAAinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...