SI3018-F-GSR Silicon Laboratories Inc, SI3018-F-GSR Datasheet - Page 55
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SI3018-F-GSR
Manufacturer Part Number
SI3018-F-GSR
Description
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3018-F-GSR.pdf
(111 pages)
Specifications of SI3018-F-GSR
Lead Free Status / Rohs Status
Supplier Unconfirmed
Si3050 + Si3018/19
5.40. Summary of Monitor Channel Com-
Communication with the Si3050 should be in the
following format:
Byte 1: Device Address Byte
Byte 2: Command Byte
Byte 3: Register Address Byte
Bytes 4-n: Data Bytes
Bytes n+1, n+2: EOM
5.41. Device Address Byte
The Device Address byte identifies which device
connected to the GCI highway receives the particular
message. This address should be the first byte sent to
the Si3050 at the beginning of every transmission
sequence. For Read commands, the address sent to
the Si3050 is the first byte transmitted in response to
the Read command before register data is transmitted.
This Device Address byte has the following structure:
The lowest programmable bit, C, has a special function.
This bit enables a register read or write, or enables a
special Channel Identification Command (CID).
C = 1: Normal command follows.
C = 0: Channel Identification Command.
The CID is a special command to identify themselves by
software. For this special command, the subsequent
command byte transmitted by the host processor must
be $00 (binary), and have no address or data bytes. The
Si3050 in turn responds with a fixed 2-byte identification
code:
Upon sending the 2-byte identification code, the Si3050
sends an EOM (MR = MX = 1) for two consecutive
frames. When A = 0, B must be 0 or the Si3050 signals
an abort due to an invalid command. In this mode, bit C
is the only other programmable bit.
A = 0: Response to CID command from the device
using channel B1 is placed in Monitor Data.
56
1
1
1
mands
0
0
0
0
1
0
A
A
1
B
0
1
0
1
0
0
1
0
C
0
0
Rev. 1.31
A = 1: Response to CID command from the device
using channel B2 is placed in Monitor Data.
When C = 1, bits A and B are channel enable bits.
When these bits are set to 1, the individual
corresponding channels receives the command in the
next
corresponding bits are set to 0 ignores the subsequent
command byte.
A = 1: Channel B1 receives the command.
A = 0: Channel B1 does not receive the command.
B = 1: Channel B2 receives the command.
B = 0: Channel B2 does not receive the command.
5.42. Command Byte
The Command byte has the following structure:
The RW bit is a register read/write bit.
RW = 0: A write is performed to the Si3050’s register.
RW = 1: A read is performed on the Si3050’s register.
The CMD[6:0] bits specify the actual command to be
performed.
CMD[6:0] = 0000001: Read or write a register on the
Si3050.
CMD[6:0] = 0000010 – 1111111: Reserved.
5.43. Register Address Byte
The Register Address byte has the following structure:
This byte contains the actual 8-bit address of the
register to be read or written.
5.44. SC Channel
The SC channel consists of six C/I bits and two
handshaking bits, MR and MX. One of these channels is
contained in every 4-byte sub-frame and is transmitted
every frame. The handshaking bits are described in the
above Monitor Channel section. The definition of the six
C/I bits depends on the direction the bits are being sent,
either transmitted to the GCI highway bus via the DTX
pin or received from the GCI highway bus via the DRX
pin.
RW
command
ADDRESS[7:0]
byte.
CMD[6:0]
The
channels
whose