SI3216-C-GM Silicon Laboratories Inc, SI3216-C-GM Datasheet - Page 49
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SI3216-C-GM
Manufacturer Part Number
SI3216-C-GM
Description
IC SLIC/CODEC 1CH 38QFN
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheet
1.SI3216-C-FT.pdf
(122 pages)
Specifications of SI3216-C-GM
Package / Case
*
Function
Subscriber Line Interface Concept (SLIC), CODEC
Interface
PCM, SPI
Number Of Circuits
1
Voltage - Supply
3.13 V ~ 5.25 V
Current - Supply
88mA
Power (watts)
700mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
Audio Tone Generation, BORSCHT Functions, FSK Generation, Ringing and Battery Voltage Generation
Product
SLIC
Supply Voltage (min)
3.13 V
Supply Current
88 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Channels
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
2.10. PCM Interface
The ProSLIC contains a flexible programmable interface
for the transmission and reception of digital PCM
samples. PCM data transfer is controlled via the PCLK
and FSYNC inputs as well as the PCM Mode Select
(direct Register 1), PCM Transmit Start Count (direct
registers 2 and 3), and PCM Receive Start Count (direct
registers 4 and 5) registers. The interface can be
configured to support from 2 to 64 16-bit timeslots in
each frame. This corresponds to PCLK frequencies of
256 kHz to 8.192 MHz in power-of-2 increments.
(768 kHz and 1.536 MHz are also available.) Timeslots
for data transmission and reception are independently
configured using the TXS and RXS registers. For the
Si3216 in wideband mode (WBE = 1, PCMF = 11, and
PCMT = 1), TXS and RXS set the correct starting point
of the data for the first timeslot within the 8 kHz frame,
and the second timeslot is set to follow 62.5 µs later.
Figure 29. Wideband PCM Operation Example, Short FSYNC, PCLK = 512 kHz (TXS/RXS = 1)
PCLK_CNT
FSYNC
PCLK
DRX
DTX
HI-Z
0
MSB
1
MSB
Bit
15
Bit
15
2
Bit
Bit
14
14
3
Bit
Bit
1
1
16
Bit
Bit
0
0
17
LSB
LSB
18
Rev. 1.0
HI-Z
Figure 29 illustrates the use of the PCM in wideband
mode. DTX data is high-impedance except for the
duration of the 16-bit PCM transmit. DTX returns to
high-impedance either on the negative edge of PCLK
during the LSB or on the positive edge of PCLK
following the LSB. This is based on the setting of the
TRI bit of the PCM Mode Select register. Tristating on
the negative edge allows the transmission of data by
multiple sources in adjacent timeslots without the risk of
driver contention. GCI timing is also supported in which
the duration of a data bit is two PCLK cycles. This mode
is also activated via the PCM Mode Select register.
Setting the TXS or RXS register greater than the
number of PCLK cycles in a sample period stops data
transmission because TXS or RXS never equals the
PCLK count.
33
MSB
34
Bit
15
Bit
15
35
Bit
14
Bit
14
48
Bit
Bit
1
1
49
Bit
Bit
0
0
LSB
HI-Z
63
Si3216
0
1
49