SI3232-G-FQ Silicon Laboratories Inc, SI3232-G-FQ Datasheet
SI3232-G-FQ
Specifications of SI3232-G-FQ
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SI3232-G-FQ Summary of contents
Page 1
... SPI bus digital interface for control. The Si3200 operates from a 3.3 V supply as well as high-voltage battery supplies up to 100 V. The Si3232 is available in a 64-pin thin quad flat package (TQFP), and the Si3200 is available in a thermally-enhanced 16-pin small-outline (SOIC) package. ...
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... Si3232 2 Preliminary Rev. 0.96 ...
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... Relay Driver Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 4.13. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.14. Audio Path Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.15. System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.16. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.17. Si3232 RAM and Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.18. System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5. 8-Bit Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6. 8-Bit Control Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 7. 16-Bit RAM Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 8 ...
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... The specified performance requires that the exposed pad be soldered to an exposed copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper surface and a large internal copper ground plane. Refer to “AN55: Dual ProSLIC™ User Guide” the Si3232 evaluation board data sheet for specific layout examples. ...
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... Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Si3232 Supply Voltage Si3200 Supply Voltage High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 ...
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... DD DD1 DD4 A Parameter Symbol V –V I –I DD1 DD4 VDD1 VDD4 Supply Current (Si3232) V Supply I DD VDD Current (Si3200) V Supply I BAT VBAT Current (Si3200) Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. 2. See “4.7.4. Ringing Power Considerations” for current and power consumption under other operating conditions. ...
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... ABIAS = 4 mA –48 V BAT Forward/reverse OHT, OBIAS = 4 mA –48 V BAT Forward/reverse OHT, OBIAS = 4 mA –70 V BAT Ringing RING rms V = –70 V, Sine Wave, 1 REN load BAT term. Preliminary Rev. 0.96 Si3232 Min Typ Max Unit — 8 — mW — 65 — mW — 70 — mW — 80 — mW — ...
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... Si3232 Table 4. AC Characteristics = ( –V 3. DD1 DD4 A Parameter TX Full Scale Output RX Full Scale Input Analog Input/Output Common Mode Voltage Overload Level Overload Compression 1 Single Frequency Distortion 2-wire to 4-wire or 4-wire to 2-wire: Signal-to-(Noise + Distortion) 2 Ratio Intermodulation Distortion 2 Gain Accuracy 2-Wire to 4-Wire or 4-Wire to 2-Wire, Gain Distortion vs ...
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... Active off-hook 200 Hz to 3.4 kHz Register-dependent OBIAS/ABIAS – Assumes ideal line impedance matching. RING = 600 Ω 600 Ω synthesized using RS register coefficients Preliminary Rev. 0.96 Si3232 Min Typ Max Unit — dBrnC — –78 –75 dBmP — — 18 dBrn 40 — ...
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... Si3232 Table 5. Linefeed Characteristics = ( –V 3. DD1 DD4 A Parameter Symbol DC Loop Current Accuracy DC Open Circuit Voltage Accuracy DC Differential Output R Resistance DC On-Hook Voltage V OHTO Accuracy—Ground Start DC Output Resistance— R ROTO Ground Start DC Output Resistance— R TOTO Ground Start Loop Closure Detect ...
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... LIM R (V – V )/I (Note 2) SAT BAT BATH OUT = 0 Ω LKG – V (Note 2) F BAT BATL Preliminary Rev. 0.96 Si3232 Min Typ Max — 8 — — ±0.75 — –1.0 — +1.5 — ±0.6 ±1.5 — ±0.1 ±0.25 Min Typ Max ⎯ ...
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... Si3232 Table 8. DC Characteristics – DD1 DD4 A Parameter Symbol High Level Input V IH Voltage Low Level Input Voltage V IL High Level Output V OH Voltage Low Level Output V OL Voltage SDITHRU Internal Pullup Resistance GPO Relay Driver R OUT Source Impedance GPO Relay Driver Sink ...
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... Test Symbol Conditions su1 su2 su1 t t su2 Figure 1. SPI Timing Diagram Preliminary Rev. 0.96 Si3232 = 20 pF) L Min Typ Max Unit 0.062 — — — — 25 — — 25 — — 20 — — — — 20 — — 25 — — 20 — — — ...
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... Si3232 Table 11. Switching Characteristics—PCLK and FSYNC Timing = ( –V 3. DD1 DD4 A Parameter PCLK Period Valid PCLK Inputs 2 FSYNC Period PCLK Duty Cycle Tolerance PCLK Period Jitter Tolerance Rise Time, PCLK Fall Time, PCLK Setup Time, FSYNC to PCLK Fall Hold Time, FSYNC to PCLK Fall ...
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... Figure 3. Si3232 Simplified Audio Path Block Diagram Fundamental 5 Output Power (dBm0 2 Fundamental Input Power (dBm0) Figure 4. Overload Compression Performance Preliminary Rev. 0.96 Acceptable Region Si3232 15 ...
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... C45 150 pF VTXP BCM3341 C46 150 pF VTXN C47 150 pF CMlevel SPI Port Figure 5. Typical Connection Diagram between Si3232 and Broadcom® BCM3341 (One SLIC channel shown: Channel “a”) 16 VRXPa SRINGDCa VRXNa SRINGACa STIPDCa SRINGDACa R40 VTXPa 20 kΩ ITIPPa ...
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... VCM 53 28 THERMa THERMb 54 27 IRINGPa IRINGPb 55 26 GND1 GND2 56 25 VDD1 VDD2 57 24 ITIPPa ITIPPb 58 23 IRINGNa IRINGNb 59 22 ITIPNa ITIPNb 60 21 SRINGDCa SRINGDCb 61 20 SRINGACa SRINGACb 62 19 STIPACa STIPACb 63 18 STIPDCa STIPDCb Preliminary Rev. 0.96 Si3232 VRXN VRXP 1 17 ...
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... Si3232 3. Bill of Materials Component C1, C2, C11, C12 100 nF, 100 V, X7R, ±20% C3, C4, C13, C14 10 nF, 100 V, X7R, ±20% C5, C6, C15, C16 1 µ X7R, ±20% C20–C25 0.1 µ Y5V C30–C33 0.1 µF, 100 V, Y5V C41–43* 3.3 nF X7R, ±20% C45–47* 150 nF X7R, ± ...
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... Si3200 is available in a thermally-enhanced 16-lead SOIC. 4.1. Linefeed Architecture The Si3232 is a low-voltage CMOS device that uses a low-cost integrated linefeed interface IC to control the high voltages required for subscriber line interfaces. Figure simplified single-ended model of the ...
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... Figure 7 and Figure 8. The constant voltage region is defined by the open-circuit voltage, V programmable from steps. The constant current region is defined by the loop current limit and is programmable from LIM 0.87 mA steps. The Si3232 exhibits a characteristic dc impedance of 320 Ω during Active mode. 20 Monitor A/D A/D A/D DSP ...
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... TIP and RING. Sense resistor R , varies OC Figure 6) measures dc line voltages on TIP and RING; , and OV capacitor C AC and RING leads to be measured. The Si3232 uses the and V that OV CM Si3200 linefeed interface IC to drive TIP and RING and to isolate the high-voltage line from the low-voltage must be OC Si3232 ...
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... Drives programmable ringing waveforms onto the subscriber loop. Reverse Active (LF[2:0] = 101). Linefeed circuitry is active, but audio paths are powered down until an off-hook condition is detected. The Si3232 will automatically enter a low-power state to reduce power consumption during on-hook standby periods. Reverse On-Hook Transmission (LF[2:0] = 110). ...
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... LIM I LIM (mA) LOOP vs. I Characteristic for Loop Start Operation LOOP Preliminary Rev. 0.96 Si3232 LSB Size Effective Range Resolution See Table 12 N/A N/A Monitor only N/A N/A N/A N/A 18–45 mA 0.875 mV 0.875 63.3 V 4.907 mV 1.005 63.3 V 4.907 mV 1.005 63.3 V 4.907 mV 1.005 ...
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... Modified Linefeed Scheme The modified linefeed scheme also allows the user to modify the apparent V boosting the linefeed voltage when the battery voltage drops below a certain level. Figure 10 illustrates a typical Si3232 application sourcing a loop from battery. For V 512 ⎞ ⎞ × ...
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... VTIP and VRING to provide the correct external voltage conditions for the calibration algorithm. The TIP and RING leads must not be connected to ground during TIP/RING leakage any calibration. Note that the channel being calibrated must be on-hook. Preliminary Rev. 0.96 Si3232 LSB Size Effective Resolution 4.907 mV 251 mV 628 mV 4.907 mV ...
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... Figure 11. Discrete Linefeed Circuit for Power Monitoring 26 protect the high-voltage circuitry against excessive power dissipation and thermal-overload conditions. The Si3232 also has the ability to prevent thermal overloads by regulating the total power inside the Si3200 or in Register each of the external bipolar transistors (if using a Value discrete linefeed circuit) ...
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... Note: The Si3200 THERM pin must be connected to the THERM a/b pin of the Si3232 in order for the Si3200 power calculation to work correctly. 4.4.6. Power Filter and Alarms The power calculated during each A/D sample period must be filtered before being compared to a user- programmable maximum-power threshold ...
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... PQ1S bit is set when a Si3200 power alarm is triggered. 4.4.8. Power Dissipation Considerations The Si3232 relies on the Si3200 to power the line from the battery supply. The PCB layout and enclosure conditions should be designed to allow sufficient ...
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... BLO sensed. Two thresholds are provided to enable battery switching with hysteresis. The BATHTH RAM location specifies the threshold at which the Si3232 will switch from the low battery, V BLO off-hook to on-hook transition. The BATLTH RAM location specifies the threshold at which the Si3232 will ...
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... BATSEL pin is used to switch between the V internal to the Si3200. The Si3232’s GPO pin is used along with the external transistor circuit to switch the V rail (the ringing voltage battery rail) onto the Si3200’s VBAT pin when ringing is enabled. The GPO signal is driven automatically by the ringing cadence provided that the RRAIL bit of the RLYCON register is set to 1 (signifying that a third battery rail is present) ...
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... VBAT V VBATH BRING 0.1 µF V VBATL BLO V BHI Figure 13. Three-Battery Switching with Si3232 Si3232 806 kΩ SVBAT R5 R9 40.2 kΩ Si3200 BATSEL D1 IN4003 Preliminary Rev. 0.96 Si3232 R101 CXT5401 Q1 R102 10 kΩ 402 kΩ R103 Q2 CXT5551 31 ...
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... Si3232 Table 18. 3-Battery Switching Components Component R101 R102 R103 4.5.1. Loop Closure Detection Loop closure detection is required to accurately signal a terminal device going off-hook during the Active or On- Hook Transmission linefeed states (forward or reverse polarity). The functional blocks required to implement a loop closure detector are shown in Figure 14, and the register set for detecting a loop closure event is provided in Table 19 ...
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... ILOOP[15: 101.09 mA LCROFFHK LCROFFHK[15: 101.09 mA LCRONHK LCRONHK[15: 101.09 mA LCRLPF LCRLPF[15:3] LCRMASK LCRMASK[15:0] –I currents. The resulting effective resolution is approximately Q1 Q4 Preliminary Rev. 0.96 Si3232 Debounce LCR Filter Interrupt LCRDBI LOOPS Logic LOOPE LSB Resolution Range Size Yes/No N/A N/A Yes/No N/A ...
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... Si3232 4.5.2. Ground Key Detection Ground key detection detects an alerting signal from the terminal equipment during the tip open or ring open linefeed states. The functional blocks required to implement a ground key detector are shown in Figure 15, and the register set for detecting a ground key event is provided in Table 22 on page 36 ...
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... Input I I Digital LONG Q2 Signal I Processor LONGLPF LFS Figure 15. Ground Key Detection Circuitry I (mA) I (mA) LOOP LONG –11 22 – LPF Debounce Filter – LONGDBI Ground Key Threshold LONGHITH LONGLOTH Preliminary Rev. 0.96 Si3232 LCR LONGHI CMHIGH LONGHI Interrupt LONGS Logic LONGE 35 ...
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... Si3232 Table 22. Register and RAM Locations used for Ground Key Detection Parameter Register/ Mnemonic Ground Key Interrupt Pend- IRQVEC2 ing Ground Key Interrupt Enable Linefeed Shadow LINEFEED Ground Key Detect Status Ground Key Detect LONGDBI Debounce Interval Longitudinal Current Sense Ground Key Threshold (high) ...
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... Ringing Generation The Si3232 is designed to provide a balanced ringing waveform with or without dc offset. The ringing frequency, cadence, waveshape, and dc offset are all register-programmable. Using a balanced ringing scheme, the ringing signal is applied to both the TIP and the RING lines using ringing waveforms that are 180° out of phase with each other. ...
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... Si3232 Table 23. Register and RAM Locations used for Ringing Generation Parameter Ringing Waveform Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Monitor Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) On-Hook Line Voltage ...
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... Once this is done, the TAEN and TIEN bits are set as desired. Ringing state is invoked by a write to the linefeed register. At the expiration of RINGTA, the Si3232 turns off the ringing waveform and goes to the on-hook transmission state. At the expiration of RINGTI, ringing is initiated again. This process continues as long as the two timers are enabled and the linefeed register remains in the ringing state ...
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... OFF OVRING Figure 19. Trapezoidal Ringing Waveform 4.7.2. Ringing DC Offset Voltage A dc offset voltage can be added to the Si3232’s ac ringing waveform by programming the RINGOF RAM address to the appropriate setting. The value of RINGOF is calculated as follows: are decimal-to-hex 4.7.3. Linefeed Overhead Voltage Considerations During Ringing ...
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... Hz. The Si3232 also provides the ability to add a dc offset component to the ringing signal and detect a ring trip event by monitoring the dc loop current flowing once the terminal equipment transitions to the off-hook state ...
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... Si3232 4.11. Loop Closure Mask The Dual ProSLIC implements a loop closure mask to ensure mode change between Ringing and Active or On-hook Transmission without causing an erroneous loop-closure detection. The loop-closure mask register, LCRMASK, should be set such that loop-closure detections are ignored for (LCRMASK x 1.25 ms/LSB) ...
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... IRQVEC2 RTRIPS IRQEN2 RTRIPE RTACTH RTACTH[15:0] RTDCTH RTDCTH[15:0] RTPER RTPER[15:0] LINEFEED LFS[2:0] LCRRPT RTP RTACDB RTACDB[15:0] RTDCDB RTDCDB[15:0] ILOOP ILOOP[15:0] Preliminary Rev. 0.96 Si3232 1 RTDCTH RTACDB/ RTDCDB 0.577(RTPER OFF 32767 See Note 2 0.577(RTPER OFF 32767 Programmable Resolution Range Yes/No N/A Enabled/Disabled ...
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... Relay Driver Considerations The Si3232 includes a general-purpose driver output for each channel (GPOa, GPOb) to drive external test relays. In most applications, the relay can be driven directly from the Si3232 with no external relay drive circuitry required. Figure 21 illustrates the internal relay driver circuitry using relay. V ...
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... Polarity Reversal The Si3232 supports polarity reversal for message- waiting functionality as well as various signaling modes. The ramp rate can be programmed for a smooth transition or an abrupt transition to accommodate different application requirements. A wink function is also provided for special equipment that responds to a smooth ramp ...
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... No transhybrid capability exists in the Si3232. 4.13.2. Pulse Metering Generation The Si3232 offers an internal tone generator suitable for generating tones above the audio frequency band. This oscillator is provided for the generation of billing tones which are typically 12 kHz or 16 kHz. The equations for ...
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... PMAMPTH PMAMPTH[15:0] PMCON ENSYNC PMCON TAEN1 PMCON TIEN1 PMCON PULSE1 Preliminary Rev. 0.96 Si3232 Description / Range (LSB Size) Sets oscillator frequency Sets oscillator amplitude 0 to PMAMPL (full amplitude 8.19 s (125 µ 8.19 s (125 µs) Interrupt status and control registers 0 to 500 mV ...
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... A Metering Figure 25. Pulse Metering Generation Block Diagram 4.14. Audio Path Processing The Si3232 is designed to connect directly to integrated access device (IAD) chipsets, such as the Broadcom BCM3341, as well as other standard codecs that use a differential audio interface. Figure 3 on page 15 illustrates the simplified block diagram for the Si3232. ...
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... Note: Therefore, the RESET pin must be held low during powerup and should only be released when both PCLK and FSYNC signals are known to be stable. 4.15.1. Interrupt Logic The Si3232 is capable of generating interrupts for the following events: Loop current/ring ground detected. Ground key detected. ...
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... The interface consists of a clock (SCLK), chip select (CSB), serial data input (SDI), and serial data output (SDO). In addition, the Si3232 includes a serial data through output (SDI_THRU) to support daisy chain operation eight devices (up to sixteen channels). The device can operate with both 8-bit and 16-bit SPI controllers ...
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... The value of the pulldown resistor depends on the capacitance seen on the SDO pin. In the case of using a single Si3232, the value of the pulldown resistor Ω . This assumes SDO pin capacitance and about load on the SDO pin. For applications using ...
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... Protected Register Bits The Si3232 has protected register bits that are meant to retain the integrity of the Si3232 circuit in the event of unintentional software register access. To access the user-protected bits, write the following sequence of data bytes to register address 87 (0x57): ...
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... SDI SDO SPI Clock SCLK CS SDO SCLK CS SDO SCLK Figure 27. SPI Daisy Chain Control Architecture Preliminary Rev. 0.96 Si3232 SDI0 SDI Channel 0 SDI1 Si3232 #1 Channel 1 SDITHRU SDI2 SDI Channel 2 SDI3 Si3232 #2 Channel 3 SDITHRU SDI4 SDI14 SDI Channel 14 SDI15 Si3232 #8 Channel 15 SDITHRU 53 ...
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... Si3232 In Figure 28, the CID field this field is decremented (LSB to MSB order), the value decrements for each SDI down the line. The BRDCST, R/W, and REG/RAM bits remain unchanged as the control word passes through the entire chain. The odd SDIs are internal to the device and represent the SDI to SDI_THRU connection between channels of the same device ...
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... SDI CONTROL SDO Figure 31. Register Write Operation via a 16-Bit SPI Port CS SCLK SDI CONTROL SDO Figure 32. Register Read Operation via a 16-Bit SPI Port ADDRESS ADDRESS Data [7:0] ADDRESS Data [7:0] Same byte repeated twice. Preliminary Rev. 0.96 Si3232 Data [7: Data [7:0] 55 ...
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... Si3232 Figures 33–36 illustrate the various cycles for accessing RAM address locations. RAM addresses are 16-bit entities; therefore the accesses always require four bytes. CS SCLK SDI CONTROL SDO Figure 33. RAM Write Operation via an 8-Bit SPI Port CS SCLK SDI SDO Figure 34. RAM Read Operation via an 8-Bit SPI Port ...
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... RAM address accesses can be scheduled for both channels without interface. 4.18. System Testing The Si3232 includes a complete suite of test tools that provide the user with the ability to test the functionality of the line card as well as detect fault conditions present on the TIP/RING pair ...
Page 58
... TIP/RING voltage can be programmed from steps. The linefeed circuitry also has the ability to generate a controlled polarity reversal. Diagnostics mode ringing generation. The Si3232 can generate an internal low-level ringing signal to test for the presence of REN without causing the terminal equipment to ring audibly. This ringing ...
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... Knowing the synthesized 2-wire impedance of the Si3232, the roll-off effect can be used to calculate the ac line capacitance. An external codec is required for this test. Preliminary Rev. 0.96 ...
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... Si3232 Ringing voltage verification. This test verifies that the desired ringing signal has been correctly applied to the TIP/RING pair and can be measured in the 8- bit monitor ADC, which senses low-frequency signals directly across T-R. Power induction measurement. This test can detect the presence of a power supply coupled onto the TIP/RING pair ...
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... CMH SPEED 4 LFS[2:0] SPI PLLFLT FSFLT PCFLT 4 PLLFAULT FSFAULT PCFAULT SRCLR Pulse Metering 4,7 7 ENSYNC TAEN1 PULSETA[15:8] PULSETA[7:0] Preliminary Rev. 0.96 Si3232 Bit 3 Bit 2 Bit 1 Bit 0 ARXMUTE ARX[1:0] CALOFFRN CALOFFTN CALDIFG CALCMG CALMADC CALDACO CALADCO CALCMBAL SDIAG SDIAGIN[2:0] 4 REV[3:0] ILIM[4:0] 4,6 ...
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... Si3232 Reg Mnemonic Description 3 Addr 32 PMTIHI Pulse Metering Oscillator Inactive Timer— High Byte 31 PMTILO Pulse Metering Oscillator Inactive Timer— Low Byte 7 POLREV Polarity Reversal Settings 103 RAMADDR RAM Address 102 RAMDATHI RAM Data— High Byte 101 RAMDATLO RAM Data— ...
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... Receive signal passed Receive signal muted. 1:0 ARX[1:0] Analog Receive Path Attenuation Stage. Selects analog receive path attenuation. See “4.14. Audio Path Processing” attenuation –3 dB attenuation –6 dB attenuation Reserved. Do not use ATX ARXMUTE R/W R/W Function Preliminary Rev. 0.96 Si3232 ARX[1:0] R/W 63 ...
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... Si3232 CALR1: Calibration 1 (Register Address 11) (Register type: Initialization) Bit D7 D6 Name CAL CALOFFR CALOFFT CALOFFRN CALOFFTN CALDIFG Type R/W Reset settings = 0x3F Bit Name 7 CAL Calibration Control/Status Bit. Begins system calibration routine Normal operation or calibration complete Calibration in progress. 6 Reserved Read returns zero. ...
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... Normal operation or calibration complete Calibration enabled or in progress. 0 CALCMBAL Common Mode Balance Calibration. Calibrates the ac longitudinal balance Normal operation or calibration complete Calibration enabled or in progress CALLKGT CALMADC CALDACO CALADCO CALCMBAL R/W R/W R/W Function Preliminary Rev. 0.96 Si3232 R/W R/W R/W 65 ...
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... Si3232 DIAG: Diagnostic Tools (Register Address 13) (Register type: Diagnostics) Bit D7 D6 Name IQ2HR IQ1HR TSTRING Type R/W R/W Reset settings = 0x00 Bit Name 7 IQ2HR Monitor ADC IQ2 High-Resolution Enable. Sets MADC to high-resolution range for IQ2 conversion MADC not set to high resolution. ...
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... PARTNUM[2:0] Type Reset settings = 0xxx Bit Name 7 Reserved Read returns zero. 6:4 PARTNUM[2:0] Part Number Identification. 000-010 = Reserved 011 = Si3232 100–111 = Reserved 3:0 REV[3:0] Revision Number Identification. 0001 = Revision A 0010 = Revision B 0011 = Revision C 0100 = Revision D 0101 = Revision E 0110 = Revision F 0111 = Revision G ...
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... Si3232 IRQ0: Interrupt Status 0 (Register Address 14) (Register type: Operational/single value instance for both channels) Bit D7 D6 Name CLKIRQ IRQ3B IRQ2B Type R R Reset settings = 0x00 Read this interrupt to indicate which interrupt status byte, from which channel, has a pending interrupt. Bit Name ...
Page 69
... Pulse Metering Inactive Timer Interrupt Pending interrupt pending Interrupt pending. 5 RINGTAS Ringing Active Timer Interrupt Pending interrupt pending Interrupt pending. 4 RINGTIS Ringing Inactive Timer Interrupt Pending interrupt pending Interrupt pending. 3:0 Reserved Read returns zero R/W R/W Function Preliminary Rev. 0.96 Si3232 ...
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... Si3232 IRQ2: Interrupt Status 2 (Register Address 16) (Register type: Operational/bits writable in GCI mode only) Bit D7 D6 Name RAMIRS Type Reset settings = 0x00 Bit Name 7:6 Reserved Read returns zero. 5 RAMIRS RAM Access Interrupt Pending interrupt pending Interrupt pending. 4 DTMFS DTMF Tone Detect Interrupt Pending. ...
Page 71
... Power Alarm Q3 Interrupt Pending interrupt pending Interrupt pending. 1 PQ2S Power Alarm Q2 Interrupt Pending interrupt pending Interrupt pending. 0 PQ1S Power Alarm Q1 Interrupt Pending interrupt pending Interrupt pending PQ5S PQ4S PQ3S R/W R/W R/W Function Preliminary Rev. 0.96 Si3232 PQ2S PQ1S R/W R/W R/W 71 ...
Page 72
... Si3232 IRQEN1: Interrupt Enable 1 (Register Address 18) (Register type: Initialization) Bit D7 D6 Name PULSTAE PULSTIE RINGTAE RINGTIE Type R/W R/W Reset settings = 0x00 Bit Name 7 PULSTAE Pulse Metering Active Timer Interrupt Enable Interrupt masked Interrupt enabled. 6 PULSTIE Pulse Metering Inactive Timer Interrupt Enable. ...
Page 73
... Ground Key Interrupt Enable Interrupt masked Interrupt enabled. 1 LOOPE Loop Closure Interrupt Enable Interrupt masked Interrupt enabled. 0 RTRIPE Ring Trip Interrupt Enable Interrupt masked Interrupt enabled DTMFE VOCTRKE LONGE R/W R/W R/W Function Preliminary Rev. 0.96 Si3232 LOOPE RTRIPE R/W R/W R/W 73 ...
Page 74
... Si3232 IRQEN3: Interrupt Enable 3 (Register Address 20) (Register type: Initialization) Bit D7 D6 Name CMBALE PQ6E Type R/W Reset settings = 0x00 Bit Name 7 CMBALE Common Mode Balance Interrupt Enable Interrupt masked Interrupt enabled. 6 Reserved Read returns zero. 5 PQ6E Power Alarm Q6 Interrupt Enable Interrupt masked. ...
Page 75
... Loop closure event has not been detected Loop closure event has been detected. Note: Detect bits are not sticky bits. Refer to interrupt status for interrupt bit history indication Function CMH SPEED VOCTST Function TR on-hook TR on-hook Preliminary Rev. 0.96 Si3232 LONGHI RTP LCR tracking is enabled ...
Page 76
... Si3232 LINEFEED: Linefeed Control (Register Address 6) (Register type: Operational) Bit D7 D6 Name LFS[2:0] Type Reset settings = 0x00 Bit Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual realtime linefeed status. Automatic operations may cause actual linefeed state transitions regardless of the Linefeed register settings (e.g., when ...
Page 77
... PLLFAULT interrupt bit is disabled. 6 FSFLT FSYNC Clock Fault Enable FSYNC interrupt bit is enabled FSYNC interrupt bit is disabled. 5 PCFLT PCM Clock Fault Enable PCM interrupt bit is enabled PCM interrupt bit is disabled. 4:0 Reserved Read returns zero R/W Function Preliminary Rev. 0.96 Si3232 ...
Page 78
... Si3232 MSTRSTAT: Master Initialization Status (Register Address 3) (Register type: Initialization/single value instance for both channels) Bit D7 D6 Name PLLFAULT FSFAULT PCFAULT Type R/W R/W Reset settings = 0x00 Bit Name 7 PLLFAULT PLL Lock Fault Status. This bit is set when the PLOCK bit transitions low, indicating loss of PLL lock. Writing 1 to this bit clears the status ...
Page 79
... Name 7:0 PULSETA[15:8] Pulse Metering Oscillator Active Timer. This register contains the upper 8 bits of the pulse metering oscillator active timer. Register 29 contains the lower 8 bits of this value TAEN1 TIEN1 PULSE1 R/W R/W R/W Function PULSETA[15:8] R/W Function Preliminary Rev. 0.96 Si3232 ...
Page 80
... Si3232 PMTALO: Pulse Metering Oscillator Active Timer—Low Byte (Register Address 29) (Register type: Initialization) Bit D7 D6 Name Type Reset settings = 0x00 Bit Name 7:0 PULSETA[7:0] Pulse Metering Oscillator Active Timer. This register contains the lower 8 bits of the pulse-metering oscillator active timer. ...
Page 81
... RAM location specified by the RAMADDR at the next memory update (WRITE operation). Writing RAMADDR loads the data stored in RAMADDR into RAMDAT only at the next memory update (READ operation POLREV VOCZERO R Function value. OC voltage RAMADDR[7:0] R/W Function Preliminary Rev. 0.96 Si3232 PREN RAMP R/W R/W R ...
Page 82
... Si3232 RAMDATHI: RAM Data—High Byte (Register Address 102) (Register type: Operational/single value instance for both channels) Bit D7 D6 Name Type Reset settings = 0x00 Bit Name 7:0 RAMDAT[15:8] RAM Data—High Byte. A write to RAMDAT followed by a write to RAMADDR places the contents of RAMDAT into a RAM location specified by the RAMADDR at the next memory update (WRITE operation) ...
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... Note: Soft reset set to a single channel of a given device causes all register space to reset to default values for that channel. Soft reset set to both channels of a given device causes a hardware reset including PLL reinitialization and RAM clear Function Function Preliminary Rev. 0.96 Si3232 RAMSTAT RESETB RESETA ...
Page 84
... Si3232 RINGCON: Ringing Configuration (Register Address 23) (Register type: Initialization) Bit D7 D6 Name ENSYNC RDACEN RINGUNB Type R R Reset settings = 0x00 Bit Name 7 ENSYNC Ringing Waveform Present Flag ringing waveform present Ringing waveform present. 6 RDACEN Ringing Waveform Sent to Differential DAC Ringing waveform not sent to differential DAC. ...
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... Ringing Oscillator Inactive Timer. This register contains the upper 8 bits of the ringing oscillator inactive timer (the silent period between ringing bursts). Register 26 contains the upper 8 bits of this value RINGTA[15:8] R/W Function RINGTA[7:0] R/W Function RINGTI[15:8] R/W Function Preliminary Rev. 0.96 Si3232 ...
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... Si3232 RINGTILO: Ringing Oscillator Inactive Timer—Low Byte (Register Address 26) (Register type: Initialization) Bit D7 D6 Name Type Reset settings = 0x00 Bit Name 7:0 RINGTI[7:0] Ringing Oscillator Inactive Timer. This register contains the lower 8 bits of the ringing oscillator inactive timer (the silent time between ringing bursts). Register 27 contains the upper 8 bits of this value. 1.25 µ ...
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... Note: Bit type “P” = user-protected bits. Refer to the protected register bit section in the text of this application note CAPB BIASEN OBIAS[1:0] R/W–P R/W–P Function Preliminary Rev. 0.96 Si3232 ABIAS[1:0] R/W–P 87 ...
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... Si3232 THERM: Si3200 Thermometer (Register Address 72) (Register type: Diagnostic/single value instance for both channels) Bit D7 D6 Name STAT SEL Type R R/W Reset settings = 0x00 Bit Name 7 STAT Si3200 Thermometer Status. Reads whether the Si3200 has shut down due to an over-temperature event. ...
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... Analog Impedance Synthesis Coefficient Disable. Enables/disables RS, ZSOHT, ZP, and ZZ coefficients Analog Analog Z 6 ZSOHT 5:4 ZP[1:0] Analog Impedance Synthesis Complex Coefficients. Refer to coefficient generation program. 3:2 Reserved 1:0 ZZ[1: ZP[1:0] R/W Function coefficients enabled. SYNTH coefficients disabled. SYNTH Preliminary Rev. 0.96 Si3232 ZZ[1:0] R/W 89 ...
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... Si3232 7. 16-Bit RAM Address Summary All internal 16-bit RAM addresses can be assigned unique values for each SLIC channel and are accessed in a similar manner as the 8-bit control registers except that the data are twice as long. In addition, one additional READ cycle is required during READ operations to accommodate the one-deep pipeline architecture. (See "4.16. ...
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... PLPF12[15:3] PLPF34[15:3] PLPF56[15:3] Pulse Metering PMAMPL[15:0] PMAMPTH[15:0] PMFREQ[15:3] PMRAMP[15:0] Power Calculations PQ1DH[15:0] PQ2DH[15:0] PQ3DH[15:0] PQ4DH[15:0] PQ5DH[15:0] PQ6DH[15:0] PSUM[15:0] 2 PTH12[15:0] 2 PTH34[15:0] 2 PTH56[15:0] RB56[15:0] Ringing RINGAMP[15:0] Preliminary Rev. 0.96 Si3232 Bit Bit Bit Bit Bit Bit Bit Type Init Init 2 Init 2 Init 2 Init 2 ...
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... Si3232 RAM Mnemonic Description Addr 57 RINGFRHI Ringing Frequency— High Byte 58 RINGFRLO Ringing Frequency— Low Byte 56 RINGOF Ringing Waveform dc Offset 60 RINGPHAS Ringing Oscillator Initial Phase 66 RTACDB AC Ring Trip Debounce Interval 64 RTACTH AC Ring Trip Detect Threshold 65 RTDCDB DC Ring Trip Debounce Interval ...
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... Programs the voltage threshold for selecting the low battery supply (VBATL). Thresh- old is compared to the RING lead voltage (normal ACTIVE mode) plus the VOV value 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution. D11 D10 R/W Function D11 D10 BATLPF[15:3] R/W Function D11 D10 R/W Function Preliminary Rev. 0.96 Si3232 ...
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... Si3232 BSWLPF: RING Voltage Filter Coefficient (RAM Address 33) Bit D15 D14 D13 D12 Name Type Reset settings = 0x00 Bit Name 15:3 BSWLPF[15:3] RING Voltage Filter Coefficient. Programs the digital low-pass filter block that filters the voltage measured on the RING lead used to determine battery switching threshold. ...
Page 95
... ADC. The input to the monitor ADC is selected by the setting in the SDIAG register (Register 13). The DIAGDCCO RAM location determines the low-pass filter coefficient used. D11 D10 DIAGAC[15:0] R/W Function D11 D10 DIAGACCO[15:3] R/W Function D11 D10 DIAGDC[15:0] R/W Function Preliminary Rev. 0.96 Si3232 ...
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... Si3232 DIAGDCCO: SLIC Diagnostics dc Filter Coefficient (RAM Address 52) Bit D15 D14 D13 D12 Name Type Reset settings = 0x00 Bit Name 15:3 DIAGDCCO[15:3] SLIC Diagnostics dc Filter Coefficient. Programs the low-pass filter coefficient used in the dc measurement result from the monitor ADC. DIAGPK: SLIC Diagnostics Peak Detector (RAM Address 55) ...
Page 97
... IRINGN (Transistor Q3) Current Measurement. Reflects the current flowing into the IRINGN pin of the Si3200 (transistor dis- crete circuit). 195.3 nA/LSB, 2’s complement. D11 D10 ILOOP[15:0] R/W Function D11 D10 IRING[15:0] R/W Function D11 D10 IRINGN[15:0] R/W Function Preliminary Rev. 0.96 Si3232 ...
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... Si3232 IRINGP: (Transistor Q2) Current Measurement (RAM Address 15) Bit D15 D14 D13 D12 Name Type Reset settings = 0x00 Bit Name 15:0 IRINGP[15:0] IRINGP (Transistor Q2) Current Measurement. Reflects the current flowing into the IRINGP pin of the Si3200 (transistor dis- crete circuit). 3.097 µ A/LSB, 2’s complement. ...
Page 99
... Loop Closure Filter Coefficient. Programs the digital low-pass filter block in the loop closure detection circuit. Refer to "4.5.1. Loop Closure Detection" on page 32 for calculation. D11 D10 ITIPP[15:0] R/W Function D11 D10 LCRDBI[15:0] R/W Function D11 D10 LCRLPF[15:3] R/W Function Preliminary Rev. 0.96 Si3232 ...
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... Si3232 LCRMASK: Loop Closure Mask Interval Coefficient (RAM Address 26) Bit D15 D14 D13 D12 Name Type Reset settings = 0x00 Bit Name 15:0 LCRMASK[15:0] Loop Closure Mask Interval Coefficient. Programs the loop closure detection mask interval. Programmable range 40.96 s, 1.25 µ s/LSB ...
Page 101
... A/LSB, 396.4 µ A effective resolution. Usable range mA. D11 D10 LCRONHK[15:0] R/W Function D11 D10 LONGDBI[15:0] R/W Function D11 D10 LONGHITH[15:0] R/W Function Preliminary Rev. 0.96 Si3232 101 ...
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... Si3232 LONGLOTH: Ground Key Removal Detection Threshold (RAM Address 28) Bit D15 D14 D13 D12 Name Type Reset settings = 0x00 Bit Name 15:0 LONGLOTH[15:0] Ground Key Removal Detection Threshold. Programs the longitudinal current threshold at which it is determined that a ground key event has been terminated 101.09 mA programmable range, 3.097 µ A/ LSB, 396.4 µ ...
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... PMAMPL[15:0] Pulse Metering Amplitude. Programs the voltage amplitude of the pulse metering signal. Refer to "4.13.2. Pulse Metering Generation" on page 46 for use. D11 D10 PLPF34[15:3] R/W Function D11 D10 PLPF56[15:3] R/W Function D11 D10 PMAMPL[15:0] R/W Function Preliminary Rev. 0.96 Si3232 103 ...
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... Si3232 PMAMPTH: Pulse Metering AGC Amplitude Threshold (RAM Address 70) Bit D15 D14 D13 D12 Name Type Reset settings = 0x00 Bit Name 15:0 PMAMPTH[15:0] Pulse Metering AGC Amplitude Threshold. Programs the voltage threshold for the automatic gain control (AGC) stage in the transmit audio path. Refer to "4.13.2. Pulse Metering Generation" on page 46 for use ...
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... Bit Name 15:0 PQ3DH[15:0] Q3 Calculated Power. Provides the calculated power in transistor Q3. Used with discrete linefeed circuitry 1.03 W range, 31.4 µ W/LSB. D11 D10 PQ1DH[15:0] R/W Function D11 D10 PQ2DH[15:0] R/W Function D11 D10 PQ3DH[15:0] R/W Function Preliminary Rev. 0.96 Si3232 105 ...
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... Si3232 PQ4DH: Q4 Calculated Power (RAM Address 47) Bit D15 D14 D13 D12 Name Type Reset settings = 0x00 Bit Name 15:0 PQ4DH[15:0] Q4 Calculated Power. Provides the calculated power in transistor Q4. Used with discrete linefeed circuitry 1.03 W range, 31.4 µ W/LSB. PQ5DH: Q5 Calculated Power (RAM Address 48) ...
Page 107
... Also programs the total power threshold when using Si3200 16.319 W programmable range, 498 µ W/LSB (0 to 34.72 W range, 1059.6 µ W/LSB in Si3200 mode). Refer to "4.4.6. Power Filter and Alarms" on page 27 for use. D11 D10 PSUM[15:0] R/W Function D11 D10 PTH12[15:0] R/W Function Preliminary Rev. 0.96 Si3232 107 ...
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... Si3232 PTH34: Q3/Q4 Power Alarm Threshold (RAM Address 38) Bit D15 D14 D13 D12 Name Type Reset settings = 0x00 Bit Name 15:0 PTH34[15:0] Q3/Q4 Power Alarm Threshold. Programs the power threshold in transistors Q3 and Q4 at which a power alarm is triggered 1.03 W programmable range, 31.4 µ W/LSB. Refer to "4.4.6. Power Filter and Alarms" ...
Page 109
... This RAM location programs the lower byte of the ringing frequency coefficient. The RINGFRHI RAM location holds the upper byte. Refer to "4.6. Ringing Generation" on page 37 for use. D11 D10 RINGAMP[15:0] R/W Function D11 D10 RINGFRHI[14:0] R/W Function D11 D10 RINGFRLO[15:3] R/W Function Preliminary Rev. 0.96 Si3232 109 ...
Page 110
... Si3232 RINGOF: Ringing Waveform dc Offset (RAM Address 56) Bit D15 D14 D13 D12 Name Type Reset settings = 0x00 Bit Name 14:0 RINGOF[14:0] Ringing Waveform dc Offset. Programs the amount of dc offset that is added to the ringing waveform during ring- ing mode 63.3 V programmable range, 4.907 mV/LSB, 1.005 V effective resolu- tion ...
Page 111
... Programs the dc loop current threshold value above which a valid ring trip event is detected. See “4.8. Ring Trip Detection” for recommended values. D11 D10 RTACTH[15:0] R/W Function D11 D10 RTDCDB[15:0] R/W Function D11 D10 RTDCTH[15:0] R/W Function Preliminary Rev. 0.96 Si3232 111 ...
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... Si3232 RTPER: Ring Trip Low-pass Filter Coefficient (RAM Address 63) Bit D15 D14 D13 D12 Name Type Reset settings = 0x00 Bit Name 15:0 RTPER[15:0] Ring Trip Low-pass Filter Coefficient. Programs the low-pass filter coefficient used in the ring trip detection circuit. See “4.8. Ring Trip Detection” for recommended values. ...
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... Holds the realtime measured loop voltage across TIP-RING 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution (251 mV effective resolution for VLOOP < 64.07 V. D11 D10 VBAT[15:0] R/W Function D11 D10 VCM[14:0] R/W Function D11 D10 VLOOP[15:0] R/W Function Preliminary Rev. 0.96 Si3232 113 ...
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... Si3232 VOC: Open Circuit Voltage (RAM Address 0) Bit D15 D14 D13 D12 Name Type Reset settings = 0x00 Bit Name 14:0 VOC[14:0] Open Circuit Voltage. Programs the TIP-RING voltage during on-hook conditions. The recommended value but can be programmed between 0 and 63.3 V. 4.907 mV/LSB, 1.005 V effective resolution ...
Page 115
... V programmable range, 4.907 mV/ LSB, 1.005 V effective resolution. D11 D10 VOCLTH[15:0] R/W Function D11 D10 VOCTRACK[15:0] R/W Function D11 D10 VOV[14:0] R/W Function Preliminary Rev. 0.96 Si3232 115 ...
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... Si3232 VOVRING: Ringing Overhead Voltage (RAM Address 6) Bit D15 D14 D13 D12 Name Type Reset settings = 0x00 Bit Name 14:0 VOVRING[14:0] Ringing Overhead Voltage. Programs the overhead voltage between the peak negative ringing level and VBATH. This value increases or decreases as the battery voltage changes in order to maintain a constant open circuit voltage but maintains its user-defined setting to ensure sufficient overhead for audio transmission when the battery voltage decreases ...
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... Pin Descriptions: Si3232 SVBATa RPOa RPIa RNIa RNOa CAPPa CAPMa QGND IREF CAPMb CAPPb RNOb RNIb RPIb RPOb SVBATb Pin #(s) Symbol 1, 16 SVBATa, SVBATb 2, 15 RPOa, RPOb 3, 14 RPIa, RPIb 4, 13 RNIa, RNIb 5, 12 RNOa, RNOb 6, 11 CAPPa, CAPPb 7, 10 CAPMa, CAPMb ...
Page 118
... Si3232 Pin #(s) Symbol 19, 62 SRINGACb, SRINGACa 20, 61 SRINGDCb, SRINGDCa 21, 60 ITIPNb, ITIPNa 22, 59 IRINGNb, IRINGNa 23, 58 ITIPPb, ITIPPa 24, 37, VDD2, VDD3, 42, 57 VDD4, VDD1 25, 38, GND2, GND3 41, 56 GND4, GND1 26, 55 IRINGPb, IRINGPa 27, 54 THERMb, THERMa 28 VCM 29, 30 VRXPb, VRXNb 31, 32 ...
Page 119
... Differential Analog Receive Input for SLIC Channel a. Exposed Die Paddle Ground. Connect to a low-impedance ground plane via topside PCB pad directly under the part. See "12. Package Outline: 64-Pin eTQFP" on page 123 for PCB pad dimensions. Preliminary Rev. 0.96 Si3232 119 ...
Page 120
... No Internal Connection —Do not connect to any electrical signal. RING Output —Connect to the RING lead of the subscriber loop. Operating Battery Voltage —Si3200 internal system battery supply. Con- nect SVBATa/b pin from Si3232 and decouple with a 0.1 µ F/100 V filter capacitor. High Battery Voltage —Connect to the system ringing battery supply. ...
Page 121
... Pin #(s) Symbol Input/ Description Output 15 ITIPN I Negative TIP Current Control —Connect to the ITIPN lead of the Si3232. 16 ITIPP I Positive TIP Current Control —Connect to the ITIPP lead of the Si3232. epad GND Exposed Die Paddle Ground. For adequate thermal management, the exposed die paddle should be sol- dered to a PCB pad that is connected to low-impedance inner and/or back- side ground planes using multiple vias. See " ...
Page 122
... Si3232 11. Ordering Guide Part Number Si3232-X-FQ Si3232-X-GQ Si3200-X-FS Si3200-X-GS Si3200-KS Si3200-BS Notes: 1. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. 2. “X” denotes product revision. 122 Package Lead Free TQFP-64 Yes TQFP-64 Yes ...
Page 123
... Package Outline: 64-Pin eTQFP Figure 39 illustrates the package details for the Si3232. Table 33 lists the values for the dimensions shown in the illustration. Figure 39. 64-Pin Thin Quad Flat Package (TQFP) Table 33. 64-Pin Package Diagram Dimensions Symbol Millimeters Min Nom A — A1 0.05 A2 0.95 1 ...
Page 124
... Si3232 13. Package Outline: 16-Pin ESOIC Figure 40 illustrates the package details for the Si3201. Table 34 lists the values for the dimensions shown in the illustration . –A– Seating Plane Figure 40. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package Table 34. Package Diagram Dimensions ...
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... AN68: 8-Bit Microcontroller Board Hardware Reference Guide AN71: Si3220/Si3225 GR-909 testing AN74: SiLINKPS-EVB User's Guide AN86: Ringing/Ringtrip Operation and Architecture on the Si3220/Si3225 Si3232PPT0-EVB Data Sheet Note: Refer to www.silabs.com for a current list of support documents for this chipset. Preliminary Rev. 0.96 Si3232 125 ...
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... L OCUMENT HANGE IST Revision 0.95 to Revision 0.96 The following changes are specific to Rev G of the Si3232 silicon: "4.5.2. Ground Key Detection" on page 34 Added descriptive text and I LONG Register , “ID: Chip Identification (Register Address 0),” on page 67 Added register value for Silicon Rev. G. ...
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... N : OTES Preliminary Rev. 0.96 Si3232 127 ...
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... Si3232 C I ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ProSLICinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...