SI3232-G-FQ Silicon Laboratories Inc, SI3232-G-FQ Datasheet - Page 32

• Manufacturer Part Number: SI3232-G-FQ
• Description: IC SLIC PROG DUAL-CH 64TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3232-G-FQ

• Function: Subscriber Line Interface Concept (SLIC)
• Interface: ISDN
• Number Of Circuits: 2
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 28mA
• Power (watts): 280mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si3232
4.5.1. Loop Closure Detection
Loop closure detection is required to accurately signal a
terminal device going off-hook during the Active or On-
Hook Transmission linefeed states (forward or reverse
polarity). The functional blocks required to implement a
loop closure detector are shown in Figure 14, and the
register set for detecting a loop closure event is
provided in Table 19. The primary input to the system is
the Loop Current Sense value provided by the voltage/
current/power monitoring circuitry and reported in the
ILOOP RAM address. The loop current (I
computed by the ISP using the equations shown below.
Refer to Figure 11 on page 26 for the discrete bipolar
transistor references used in the equation below (Q1,
Q2, Q5 and Q6 – note that the Si3200 has
corresponding MOS transistors). The same I
equation applies to the discrete bipolar linefeed as well
as the Si3200 linefeed device. The following equation is
conditioned by the CMH status bit in register LCRRTP
and by the linefeed state as indicated by the LFS field in
the LINEFEED register.
If the CMHITH (RAM 36) threshold is exceeded, the
CMH bit is 1, and I
FORWARD-ACTIVE and TIP-OPEN states, or I
forced to zero in the REVERSE-ACTIVE and RING-
OPEN states. The other currents in the equation are
allowed to contribute normally to the I
32
I
loop
=
=
I
I
--------------------------------------------------- - in all other states
Q1
Q1
–
–
I
I
Q6
Q6
+
+
2
I
I
Q5
Q5
Component
–
–
I
I
Q2
Q1
R101
R102
R103
Q2
D1
Q1
Q2
in TIP-OPEN or RING-OPEN
is forced to zero in the
Table 18. 3-Battery Switching Components
LOOP
402 kΩ, 1/10 W, ±1%
10 kΩ, 1/10 W, ±5%
200 V, 200 mA
value.
1/10 W, ±5%
100 V NPN
100 V PNP
LOOP
Preliminary Rev. 0.96
Value
Q2
LOOP
) is
is
The conditioning due to the CMH bit (LCRRTP Register)
and LFS field (LINEFEED Register) states can be
summarized as follows:
The output of the Input Signal Processor is the input to a
programmable digital low-pass filter, which can be used
to remove unwanted ac signal components before
threshold detection.
The low-pass filter coefficient is calculated using the
following equation and is entered into the LCRLPF RAM
location.
LCRLPF = [(2
Where f is the desired cutoff frequency of the filter.
The programmable range of the filter is from 0h (blocks
all signals) to 4000h (unfiltered). A typical value of 10
(0A10h) is sufficient to filter out any unwanted ac
artifacts while allowing the dc information to pass
through the filter.
The output of the low-pass filter is compared to a
programmable threshold, LCROFFHK. Hysteresis is
enabled
LCRONHK, to detect the loop going to an OPEN or on-
hook state. The threshold comparator output feeds a
programmable debounce filter. The output of the
debounce filter remains in its present state unless the
input remains in the opposite state for the entire period
of time programmed by the loop-closure debounce
interval, LCRDBI. There is also a loop-closure mask
interval, LCRMASK, that is used to mask transitions
caused when an internal ringing burst (no dc offset)
ends in the presence of a high REN load. If the
debounce interval has been satisfied, the LCR bit will be
set to indicate that a valid loop closure has occurred.
IQ1 = 0 if (CMH = 1 AND (LFS = 1 OR LFS = 3))
IQ2 = 0 if (CMH = 1 AND (LFS = 5 OR LFS = 7))
2.4 kΩ for V
by
3.9 kΩ for V
CXT5401 or similar
CXT5551 or similar
IN4003 or similar
π
f x 4096)/800] x 2
programming
Comments
DD
DD
= 3.3 V
= 5 V
a
3
second
threshold,