SI3232-BQ Silicon Laboratories Inc, SI3232-BQ Datasheet - Page 76

• Manufacturer Part Number: SI3232-BQ
• Description: IC SLIC PROG DUAL-CH 64TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3232-BQ

• Package / Case: *
• Function: Subscriber Line Interface Concept (SLIC)
• Interface: ISDN
• Number Of Circuits: 2
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 28mA
• Power (watts): 280mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Product: SLIC
• Supply Voltage (min): 3.13 V
• Supply Current: 28 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Si3232
MSTRSTAT: Master Initialization Status (Register Address 3)
(Register type: Initialization/single value instance for both channels)
Reset settings = 0x00
76
Name PLLFAULT FSFAULT PCFAULT
Type
Bit
Bit
7
6
5
4
3
2
1
0
PLLFAULT
PCFAULT
FSFAULT
SRCLR
PLOCK
FSDET
PCVAL
FSVAL
Name
R/W
D7
PLL Lock Fault Status.
This bit is set when the PLOCK bit transitions low, indicating loss of PLL lock. Writing 1 to
this bit clears the status.
0 = PLL lock is valid.
1 = PLL has lost lock.
FSYNC Clock Fault Status.
This bit is set when the FSVAL and FSDET bits transition low, indicating loss of valid
FSYNC signal or invalid FSYNC-to-PCLK ratio. Writing 1 to this bit clears the status.
0 = Correct FSYNC to PCLK ration present.
1 = FSYNC to PCLK ratio lost.
PCM Clock Fault Status.
This bit will be set when the PCVAL bit transitions low. Writing 1 to this bit clears the status.
0 = Valid PCLK signal present.
1 = No valid PCLK signal present.
SRAM Clear Status Detect.
0 = SRAM clear operation not initiated or in progress.
1 = SRAM clear operation has completed.
PLL Lock Detect.
Indicates the internal PLL is locked relative to FSYNC.
0 = PLL has lost lock relative to FSYNC.
1 = PLL locked relative to FSYNC.
FSYNC to PCLK Ratio Detect.
Indicates a valid FSYNC to PCLK ratio has been detected.
0 = Invalid FSYNC to PCLK ratio detected.
1 = Correct FSYNC to PCLK ratio present.
FSYNC Clock Valid.
Indicates that a minimum valid FSYNC signal is present.
0 = FSYNC signal is not valid.
1 = FSYNC signal is present.
PCM Clock Valid.
Indicates that a minimum valid PCLK signal is present.
0 = PCLK signal is ≤ 128 kHz.
1 = PCLK signal is ≥ 128 kHz.
R/W
D6
R/W
D5
SRCLR
Preliminary Rev. 0.95
D4
R
PLOCK
D3
R
Function
FSDET
D2
R
FSVAL
D1
R
PCVAL
D0
R