DS21Q50L-W+ Maxim Integrated Products, DS21Q50L-W+ Datasheet - Page 29

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DS21Q50L-W+

Manufacturer Part Number
DS21Q50L-W+
Description
TXRX E1 QUAD CLK/DATA 100LQFP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS21Q50L-W+

Function
Transceiver
Interface
E1
Number Of Circuits
4
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
230mA
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Operating Temperature
-
Other names
90-21Q50+LW0
4.3 Automatic Alarm Generation
The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS
generation is enabled (CCR2.5 = 1), the device monitors the receive framer to determine if any of the
following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or
loss-of-receive carrier (or signal). If any one (or more) of the above conditions is present, then the framer
forces an AIS alarm.
When automatic RAI generation is enabled (CCR2.4 = 1), the framer monitors the receive to determine if
any of the following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones)
reception, or loss-of-receive carrier (or signal), or if CRC4 multiframe synchronization cannot be found
within 128ms of FAS synchronization (if CRC4 is enabled). If any one (or more) of the above conditions
is present, the framer transmits an RAI alarm. RAI generation conforms to ETS 300 011 specifications
and a constant remote alarm is transmitted if the DS21Q50 cannot find CRC4 multiframe synchronization
within 400ms as per G.706.
Register Name:
Register Description:
Register Address:
Bit
Name
NAME
TCM4
TCM3
TCM2
TCM1
TCM0
LIAIS
RLB
LLB
RLB
7
BIT
7
6
5
4
3
2
1
0
LLB
Remote Loopback. See Section
0 = loopback disabled
1 = loopback enabled
Local Loopback. See Section
0 = loopback disabled
1 = loopback enabled
Line Interface AIS Generation Enable
0 = allow normal data to be transmitted at TTIP and TRING
1 = force unframed all ones to be transmitted at TTIP and TRING at the MCLK rate
Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit
channel data appear in the TDS0M register. See Section
Transmit Channel Monitor Bit 3
Transmit Channel Monitor Bit 2
Transmit Channel Monitor Bit 1
Transmit Channel Monitor Bit 0. LSB of the channel decode.
6
CCR3
Common Control Register
14 Hex
LIAIS
5
TCM4
4
4.5
29 of 87
4.4
TCM3
for details.
3
for details.
FUNCTION
TCM2
2
TCM1
6
1
or details.
TCM0
0

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