DS21Q50L-W+ Maxim Integrated Products, DS21Q50L-W+ Datasheet - Page 37

• Manufacturer Part Number: DS21Q50L-W+
• Description: TXRX E1 QUAD CLK/DATA 100LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q50L-W+

• Function: Transceiver
• Interface: E1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 230mA
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Operating Temperature: -
• Other names: 90-21Q50+LW0

Register Name:
Register Description:
Register Address:
Bit
Name
PRBSD
NAME
RCMF
LOTC
RMF
TMF
RAF
TAF
SEC
RMF
7
BIT
7
6
5
4
3
2
1
0
RAF
Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is enabled or not)
on receive multiframe boundaries.
Receive Align Frame. Set every 250µs at the beginning of align frames. Used to alert the
host that Si and Sa bits are available in the RAF and RNAF registers.
Transmit Multiframe. Set every 2ms (regardless if CRC4 is enabled) on transmit
multiframe boundaries.
One-Second Timer. Set on increments of one second based on RCLK. If CCR2.7 = 1, this
bit is set every 62.5ms instead of once a second.
Transmit Align Frame. Set every 250µs at the beginning of align frames. Used to alert the
host that the TAF and TNAF registers need to be updated.
Loss-of-Transmit Clock. Set when the TCLK pin has not transitioned for one channel time
(or 3.9ms).
Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries; continues to be set every
2ms on an arbitrary boundary if CRC4 is disabled.
Pseudorandom Bit-Sequence Detect. When receive PRBS is enabled, this bit is set when
the 2
framed, unframed, or in a specific time slot.
6
SR2
Status Register 2
0B Hex
15
- 1 PRBS pattern is detected at RPOS and RNEG. The PRBS pattern can be
TMF
5
SEC
4
37 of 87
TAF
3
FUNCTION
LOTC
2
RCMF
1
PRBSD
0