DS3174 Maxim Integrated Products, DS3174 Datasheet - Page 36
DS3174
Manufacturer Part Number
DS3174
Description
IC QUAD DS3/E3 TXRX 400-PBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3171N.pdf
(234 pages)
Specifications of DS3174
Function
Single-Chip Transceiver
Interface
DS3, E3
Number Of Circuits
4
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
725mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
400-BGA
Includes
DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
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8.3 Pin Functional Timing
8.3.1
8.3.1.1
There is no suggested time alignment between the TXPn, TXNn and TX LINE signals and the TLCLKn clock signal.
The TX DATA signal is not a readily available signal, it is meant to represent the data value of the other signals.
The TXPn and TXNn signals are only available when the line is in B3ZS/HDB3 or AMI mode and the LIU is
enabled. The TPOSn, TNEGn and TLCLKn signals are only available when the line is in B3ZS/HDB3 or AMI mode
and the transmit line pins are enabled. The TPOSn, TNEGn and TLCLKn pins can be enabled at the same as the
LIU is enabled.
The TPOSn and TNEGn signals change a small delay after the positive edge of the reference clock if the clock pin
is not inverted; otherwise they change after the negative edge. The TLCLKn clock pin is the clock reference
typically used for the TPOSn and TNEGn signals, but they can be time referenced to the TCLKIn, TCLKOn,
RLCLKn or RCLKOn clock pins. The TPOSn and TNEGn pins can be inverted, but the polarity of TXPn and TXNn
cannot be inverted.
TXPn and TXNn are differential analog output pins. They are biased around ½ VDD and pulse above and below
the bias voltage by about 1 Volt. These signals are connected to the windings of a 1:2 step down transformer and
the other winding of the transformer creates the TX LINE signal. The TX LINE signal is a bipolar signal that pulses
about 1 Volt positive and 1 Volt negative above and below ground (0 volts). See
external connections.
Figure 8-1
Figure 8-1. TX Line IO B3ZS Functional Timing Diagram
(TX DATA)
(TX LINE)
TLCLK
TNEG
TPOS
Line IO
TXN
TXP
B3ZS/HDB3/AMI Mode Transmit Pin Functional Timing
and
Figure 8-2
0 V
BIAS V
+
show the relationship between the analog and the digital outputs.
-
B
B
B
B
V
V
V
V
36
B3ZS CODEWORD
Figure 1-1
for a diagram of the
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