M-8870-01SM Clare, M-8870-01SM Datasheet

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M-8870-01SM

Manufacturer Part Number
M-8870-01SM
Description
IC RECEIVER DTMF CMOS LP 18-SOIC
Manufacturer
Clare
Datasheet

Specifications of M-8870-01SM

Function
DTMF Receiver
Number Of Circuits
1
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
3mA
Power (watts)
35mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
*
Includes
Decoder, Dial Tone Suppression
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Interface
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M-8870-01SM
Manufacturer:
IXYS Integrated Circuits Division
Quantity:
2 912
Part Number:
M-8870-01SMTR
Manufacturer:
IXYS Integrated Circuits Division
Quantity:
236
Block Diagram
DS-M8870-R3
Features
Applications
Pin Configuration
Low Power Consumption
Adjustable Acquisition and Release Times
Central Office Quality and Performance
Power-down and Inhibit Modes (-02 only)
Inexpensive 3.58 MHz Time Base
Single 5 Volt Power Supply
Dial Tone Suppression
Telephone switch equipment
Remote data entry
Paging systems
Personal computers
Credit card systems
www.clare.com
Ordering Information
Description
The M-8870 is a full DTMF Receiver that integrates
both bandsplit filter and decoder functions into a single
18-pin DIP or SOIC package. Manufactured using
CMOS process technology, the M-8870 offers low
power consumption (35 mW max) and precise data
handling. Its filter section uses switched capacitor
technology for both the high and low group filters and
for dial tone rejection. Its decoder uses digital counting
techniques to detect and decode all 16 DTMF tone
pairs into a 4-bit code. External component count is
minimized by provision of an on-chip differential input
amplifier, clock generator, and latched tri-state inter-
face bus. Minimal external components required
include a low-cost 3.579545 MHz color burst crystal, a
timing resistor, and a timing capacitor.
The M-8870-02 provides a “power-down” option
which, when enabled, drops consumption to less
than 0.5 mW. The M-8870-02 can also inhibit the
decoding of fourth column digits (see Tone Decoding
table on page 5).
M-8870-01
M-8870-01SM
M-8870-01SMTR
M-8870-02
M-8870-02SM
M-8870-02T
Part #
Description
18-pin plastic DIP
18-pin plastic SOIC
18-pin plastic SOIC, tape and reel
18-pin plastic DIP, power-down,
option
18-pin plastic SOIC, power-down,
option
18-pin plastic SOIC, power-down
option, tape and reel
DTMF Receiver
M-8870
1

M-8870-01SM Summary of contents

Page 1

... Tone Decoding table on page 5). Ordering Information Part # Description M-8870-01 18-pin plastic DIP M-8870-01SM 18-pin plastic SOIC M-8870-01SMTR 18-pin plastic SOIC, tape and reel M-8870-02 18-pin plastic DIP, power-down, option M-8870-02SM 18-pin plastic SOIC, power-down, option M-8870-02T ...

Page 2

... Functional operation of the device at these or V -0.3, VDD +0.3 any other conditions beyond those indicated in the opera- SS tional sections of this data sheet is not implied. Exposure max the device to the absolute maximum ratings for an extend- -40° 85°C ed period may degrade the device and effect its reliability. ...

Page 3

... Before a decoded tone pair is registered, the receiver checks for a valid signal duration (referred to as char- acter-recognition-condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes VC (see block diagram on page 1) to rise as the capacitor discharges. Provided that sig- ...

Page 4

... A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St. (See Common Crystal Connection on page 5). ...

Page 5

... C 941 1633 D ANY ANY ANY L = logic low logic high high impedance Differential Input Configuration Rev single-ended configuration, the input pins are connected as shown in the Single - Ended Input Configuration on page 3 with the op-amp connected for unity gain and V REF The Differential Input Configuration bellow permits ...

Page 6

... Minimum signal acceptance level is measured with specified maximum frequency deviation. 11. Input pins defined as IN+, IN-, and OE. 12. External voltage source used to bias V . REF 13. This parameter also applies to a third tone injected onto the power supply. 14. Referenced to Single - Ended Input Configuration on page 3. Input DTMF tone level at -28 dBm. 6 Symbol Min Typ* Max ...

Page 7

... Outputs switched to high impedance state. (E) Tone # detected, tone duration valid, tone decoded and latched in outputs (currently high impedance). (F) Acceptable dropout of tone # tone absent duration invalid, outputs remain latched. (G) End of tone # detected, tone absent duration valid, outputs remain latched until next valid tone. Explanation of Symbols VIN DTMF composite input signal ...

Page 8

... M-8870 Figure 9 Mechanical Dimensions 8 Tolerances for 18 - pin Dip Inches Min Max A - .210 A1 .015 b .014 .022 b2 .045 .070 C .008 .014 D .880 .920 E .300 .325 E1 .240 .280 e .100 BSC ec 0° 15° L .115 .150 Tolerances for 18 - pin Dip Inches Min Max A .0926 .1043 A1 ...

Page 9

... Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-M-8870-R3 ©Copyright 2001, Clare, Inc. ...

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