SI3220-FQ Silicon Laboratories Inc, SI3220-FQ Datasheet - Page 107

• Manufacturer Part Number: SI3220-FQ
• Description: IC SLIC/CODEC DUAL-CH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3220-FQ

• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: GCI, PCM, SPI
• Number Of Circuits: 2
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 65mA
• Power (watts): 941mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
• Product: Telecom
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 0.96 to Revision 1.0
The Following Changes are Specific to Rev. G of the
Si3220/25 Silicon:
The Following Changes are Corrections and Omis-
sions to Rev. 0.96:
Figure 21 on page 42:
"Loop Closure Detection" on page 42:
"Ground Key Detection" on page 43:
Added Table 25, “Settings for Ground Key Example,”
on page 44.
Added Table 26, “State Transitions During Ground
Key Detection,” on page 44.
"TXEQ/RXEQ Equalizer Blocks" on page 67.
Table 49 on page 90:
"Dual ProSLIC® Selection Guide" on page 2
Table 6, “Linefeed Characteristics,” on page 12
Table 12, “Switching Characteristics—SPI,” on
page 16:
Figure 1, “SPI Timing Diagram,” on page 16:
Figures 7, 8, 9, and 10 on pages 21–23:
Figure 11, “AC Signal Path Block Diagram for a
Single Channel,” on page 24:
Figure 12, “Si3220 Application Circuit Using Dual
Battery Supply,” on page 25:
Figure 13, “Si3225 Application Circuit Using
Centralized Ringer and Secondary Battery Supply,”
on page 26:
Table 15, “Si3220 + Si3200 External Component
Values,” on page 27
location.
switch (ZSDIS).
Added CMH input to ISP block.
Added IQ1, IQ2, IQ5 and IQ6 inputs to ISP block.
Showed ILOOP as output of ISP block.
Added ILOOP equation and explanatory text.
Added I
Removed note concerning TXEQCO0 coefficient.
Added “Mirrored Register Bit(s)” column.
Added lead-free packages.
Corrected R
Added td1, td4 and tcs.
Changed tsu1 from 15ns. (min.) to 25ns. (min.).
Added td1 and tcs.
Corrected Y-axis labels
Corrected digital impedance synthesis block (ZD)
Correctly labeled analog impedance synthesis disable
Deleted modem tone detection block from the RX path.
Added resistors R20, R21, R22, R23, R24 and 25
Added resistors R23, R24, R25, R26, R27 and R28.
Added resistors R20–R25.
LONG
LOOP
equation and explanatory text.
specification.
Rev. 1.0
Table 16, “Si3225 + Si3200 External Component
Values,” on page 27
"Adaptive Linefeed" on page 32
Figure 41, “SPI Daisy-Chain Mode,” on page 70:
page 104:
Deleted duplicate ordering guide from back of
document.
"Silicon Labs Si3220/25 Support Documentation" on
Replaced figures 16, 17, and 18 with new Figure 16 and
Added resistors R23–R28.
Improved text describing loop start and ground start
operation.
Figure 17.
Added missing connection between CPU SDO pin and
Dual ProSLIC SDI pin.
Added AN88: Dual ProSLIC Line Card Design.
Added AN91: Si3200 Power Offload Circuit.
Added AN196: Dual ProSLIC Digital Impedance
Synthesis
Si3220/Si3225
107