NOIL1SE3000A-GDC ON Semiconductor, NOIL1SE3000A-GDC Datasheet - Page 10

• Manufacturer Part Number: NOIL1SE3000A-GDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SE3000A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

64 PGA and ADC channels.
processing, PGA, and ADC stages. The total latency is 44
high-speed input clock delays. The output synchronization
signals from the LVDS sync channel factor in this latency.
Programmable Dark Level
level. This analog voltage corresponds with the all-zero
output of the ADC. This dark level is tuned to optimally use
the ADC range.
distribution. This distribution is visible in a dark image as
the FPN. The spread on the distribution is influenced by the
dark current and temperature. Typically the spread is
100 mV peak-to-peak.
several parameters:
•
•
•
dark level. The offset is in the order of magnitude of 200 mV.
Table 9. PROGRAMMABLE AMPLIFIERS GAIN SETTINGS
The gain is set through bits 2:0 in register 73 (decimal).
The gain register controls the gain setting globally for all
A latency (delay) is incurred for the analog signal
An SPI-controlled DAC provides the PGA with a dark
The dark level coming from the pixels follow a Gaussian
The average dark level of this distribution depends on
The combination of these parameters adds an offset to the
The processing corner
Tolerances on the pixel power supplies (Vpix, Vreset,
Vmem_l, and Vmem_h)
Pixel timing
Bit 2
0
0
0
0
1
1
1
Register Address d73
Bit 1
0
0
1
1
0
0
1
Figure 10. Analog Frontend and ADC Concept
Bit 0
0
1
0
1
0
1
x
http://onsemi.com
10
dark level is mapped inside the range of the ADC. To
optimally use the input range of the ADC, the spread on the
dark level is mapped as close as possible to the high level of
the ADC’s input range.
DAC is 1.5 V. This ensures that the spread on the dark level
is completely mapped in the ADC range. The startup DAC
dark level is not optimal. By taking a dark image after
startup, the offset on the dark image histogram is measured.
The offset from the optimal case is subtracted from the dark
level coming from the DAC. This places the dark level
distribution optimally inside the range of the ADC. Follow
this procedure after every change in operation condition
such as temperature, FOT timing, and ROT.
Analog- to-Digital Converters
approximately 25.75 mega samples per second (MSPS).
Two ADCs are combined to provide digitized data to one of
the 32 LVDS serialization channels. One of the ADC pair
converts data from an ‘odd kernel’ of the LUPA3000 pixel
array, the other from an ‘even kernel’. LUPA3000 only
processes the eight MSBs of the converter to realize an
improved noise performance 8-bit converter.
To allow off-chip FPN calibration, the full spread on the
The default startup value of the dark level coming from the
LUPA3000 includes 64 pipelined 9-bit ADCs operating at
Gain Level
2.25x
1.5x
2.0x
3.0x
4.0x
3.0x
1x
POR default value
Do not use (Redundant gain codes)
Comments