CP82C50A-5Z Intersil, CP82C50A-5Z Datasheet - Page 16
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CP82C50A-5Z
Manufacturer Part Number
CP82C50A-5Z
Description
IC ASYNC COMM ELEMENT UART 40DIP
Manufacturer
Intersil
Datasheet
1.CS82C50A-5Z.pdf
(25 pages)
Specifications of CP82C50A-5Z
Features
Single Chip UART/BRG
Number Of Channels
1, UART
Protocol
RS232C
Voltage - Supply
4.5 V ~ 5.5 V
With Parallel Port
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Through Hole
Package / Case
40-DIP (0.600", 15.24mm)
Rohs Compliant
YES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CP82C50A-5Z
Manufacturer:
Intersil
Quantity:
342
Programming
The 82C50A is programmed by the control registers LCR,
lER, DLL and DLM, and MCR. These control words define
the character length, number of stop bits, parity, baud rate,
and modem interface.
While the control registers can be written in any order, the
lER should be written to last because it controls the interrupt
enables. Once the 82C50A is programmed and operational,
these registers can be updated any time the 82C50A is not
transmitting or receiving data.
The control signals required to access 82C50A internal
registers are shown below.
Software Reset
A software reset of the 82C50A is a useful method for
returning to a completely known state without a system
reset. Such a reset consists of writing to the LCR, Divisor
Latches, and MCR registers. The LSR and RBR registers
should be read prior to enabling interrupts in order to clear
out any residual data or status bits which may be invalid for
subsequent operation.
Crystal Operation
The 82C50A crystal oscillator circuitry is designed to operate
with a fundamental mode, parallel resonant crystal. Table 8
shows the required crystal parameters and crystal circuit
configuration, respectively.
When using an external clock source, the XTAL1 input is
driven and the XTAL2 output is left open. Power
consumption when using an external clock is typically 50%
of that required when using a crystal. This is due to the
sinusoidal nature of the drive circuitry when using a crystal.
16
82C50A
The maximum frequency of the 82C50A is 10MHz with an
external clock or a crystal attached to XTAL1 and XTAL2.
Using the external clock or crystal, and a divide by one
divisor, the maximum BAUDOUT is 10MHz, and the
maximum data rate is 625Kbps.
Frequency
Type of Operation
Load Capacitance (CL)
R
SERIES
FIGURE 2. TYPICAL CRYSTAL OSCILLATOR CIRCUIT
TABLE 8. TYPICAL CRYSTAL OSCILLATOR CIRCUIT
PARAMETER
(Max)
CL
CL
XTAL
RS
XTAL1
XTAL2
1.0 to 10MHz
Parallel Resonant, Fundamental
Mode
20 or 32pF (Typ)
100Ω (f = 10MHz, CL = 32pF)
200Ω (f = 10MHz, CL = 20pF)
PIN 16
PIN 17
82C50A
GENERATOR
BAUD RATE
LOGIC
August 24, 2006
TO
FN2958.5