CDP1826CE Intersil Corporation, CDP1826CE Datasheet

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CDP1826CE

Manufacturer Part Number
CDP1826CE
Description
CMOS 64-Word x 8-Bit Static RAM
Manufacturer
Intersil Corporation
Datasheet
March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• Ideal for Small, Low-Power RAM Memory Require-
• Interfaces
• Daisy Chain Feature to Further Reduce External
• Multiple Chip-Select Inputs for Versatility
• Single Voltage Supply
• No Clock or Precharge Required.
Ordering Information
Pinout
PDIP
ments in Microprocessor and Microcomputer Applica-
tions
Without Additional Address Decoding
Decoding Needs
PACKAGE
BUS 0
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
with
CS1
CS2
V
SS
TEMP. RANGE
-40
10
11
o
1
2
3
4
5
6
7
8
9
CDP1826C (PDIP)
CDP1800-Series
C to +85
TOP VIEW
|
o
Copyright
C
CDP1826CE
PART NUMBER
22
21
20
19
18
17
16
15
14
13
12
©
V
A0
CS/A5
A1
A2
A3
A4
TPA
MRD
MWR
CEO
Intersil Corporation 1999
DD
Microprocessors
E22.4
PKG.
NO.
6-47
Description
The CDP1826C is a general purpose, fully static, 64-word x
8-bit random-access memory, for use in CDP1800-series or
other microprocessor systems where minimum component
count and/or price performance and simplicity in use are
desirable.
The CDP1826C has 8 common data input and data-output
terminals with three-state capability for direct connection to a
standard bidirectional data bus. Two chip-select inputs - CS1
and CS2 - are provided to simplify memory-system expan-
sion. An additional select pin, CS/A5, is provided to enable
the CDP1826C to be selected directly from the CDP1800
multiplexed address bus without additional latching or
decoding. In an 1800 system, the CS/A5 pin can be tied to
any MA address line from the CDP1800 processor. A TPA
input is provided to latch the high-order bit of this address
line as a chip-select for the CDP1826C. If this CS/A5 input is
latched high, and if CS = 1 and CS2 = 0 at the appropriate
time in the memory cycle, the CDP1826C will be enabled for
writing or reading. In a non-1800 system, the TPA pin can be
tied high, and the CS/A5 pin can be used as a normal
address input.
The six input-address buffers are gated with the chip-select
function to reduce standby current when the device is dese-
lected, as well as to provide for a simplified power down
mode by reducing address buffer sensitivity to long fall times
from address drivers which are being powered down.
Two memory control signals, MRD and MWR, are provided
for reading from the writing to the CDP1826C. The logic is
designed so that MWR overrides MRD, allowing the chip to
be controlled from a single R/W.
A CHIP ENABLE OUTPUT is provided for daisy-chaining to
additional memories or I/O devices. This output is high
whenever the chip-select function selects the CDP1826C,
which deselects any other chip which has its CS input con-
nected to the CDP1826C CEO output. The connected chip is
selected when the CDP1826C is deselected and the MRD
input is low. Thus, the CEO is only active for a read cycle
and can be setup so that a CEO of another device can feed
the MRD of the CDP1826C, which in turn selects a third chip
in the daisy chain.
The CDP1826C has a recommended operating voltage of
4.5V to 5.5V and is supplied in 22 lead dual-in-line plastic
packages (E suffix). The CDP1826C is also available in chip
form (H suffix).
CDP1826C
CMOS 64-Word x 8-Bit
File Number
Static RAM
1311.2

Related parts for CDP1826CE

CDP1826CE Summary of contents

Page 1

... Daisy Chain Feature to Further Reduce External Decoding Needs • Multiple Chip-Select Inputs for Versatility • Single Voltage Supply • No Clock or Precharge Required. Ordering Information PACKAGE TEMP. RANGE o o PDIP - +85 C CDP1826CE Pinout CDP1826C (PDIP) TOP VIEW BUS BUS 1 3 BUS 2 BUS BUS 4 ...

Page 2

ADDR BUS TPA RAM ROM CDP1826C MRD CEO 8-BIT BIDIRECTIONAL DATA BUS FIGURE 1. TYPICAL CDP1802 MICROPROCESSOR SYSTEM CDP1826C CLEAR WAIT MRD ADDR BUS TPB TPA Q CPU SCO SCI CDP1800 SERIES INTERRUPT MRD DMA - IN ...

Page 3

Absolute Maximum Ratings DC Supply Voltage Range (All Voltages Referenced to V Terminal) SS CDP1826C ...

Page 4

Signal Descriptions A0 - A4, CS/A5 (Address Inputs): These inputs must be stable prior to a write operation, but may change asynchro- nously during Read operations 1800 system, the multiplexed high-order address bit at pin CS/A5 can be ...

Page 5

CLOCK A5 TPA MRD CEO BUS RAM CYCLE CS1 = 1, CS2 = 0 FUNCTION CDP1800 Mode Write Read Deselect Deselect Deselect Deselect Deselect Non-CDP1800 Mode Write Read Deselect Deselect Deselect NOTE: 1. For CDP1800 Mode, refers to high ...

Page 6

Dynamic Electrical Specifications PARAMETER READ - CYCLE TIMES (FIGURES 4 AND 5) Address to TPA Setup Address to TPA Hold Access from Address Change TPA Pulse Width Output Valid from MRD Access from Chip Select CEO Delay from TPA Edge ...

Page 7

HIGH ORDER xxxxx ADDRESS BYTE xxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx MRD xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx CS1 CS2 xxxxxxxxxxxxxxxxxxxxxx BUS FIGURE 5. TIMING WAVEFORMS FOR READ-CYCLE 2 (TPA HIGH) Dynamic Electrical Specifications PARAMETER WRITE - CYCLE TIMES (FIGURES ...

Page 8

HIGH ORDER xxxxxx ADDRESS BYTE xxxxxx t t ASH AH TPA t PAW MWR xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx CS1 • CS2 xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx BUS xxxxxxxxxxxx FIGURE 6. TIMING WAVEFORMS FOR WRITE-CYCLE 1 xxxxx xxxxx ...

Page 9

... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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