CD82C52 Intersil Corporation, CD82C52 Datasheet

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CD82C52

Manufacturer Part Number
CD82C52
Description
CMOS Serial Controller Interface
Manufacturer
Intersil Corporation
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CD82C52
Manufacturer:
INTERSIL
Quantity:
76
Part Number:
CD82C52
Manufacturer:
INTERSIL
Quantity:
345
Part Number:
CD82C52
Manufacturer:
INTERS
Quantity:
394
March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• Single Chip UART/BRG
• DC to 16MHz (1M Baud) Operation
• Crystal or External Clock Input
• On-Chip Baud Rate Generator - 72 Selectable Baud
• Interrupt Mode with Mask Capability
• Microprocessor Bus Oriented Interface
• 80C86 Compatible
• Single +5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . 1mA/MHz Typ
• Modem Interface
• Line Break Generation and Detection
• Operating Temperature Range:
Pinouts
Rates
- C82C52 . . . . . . . . . . . . . . . . . . . . . . . . . .0
- I82C52 . . . . . . . . . . . . . . . . . . . . . . . . . -40
- M82C52 . . . . . . . . . . . . . . . . . . . . . . . -55
WR
RD
OX
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
IX
10
11
12
13
14
1
2
3
4
5
6
7
8
9
82C52 (PDIP, CERDIP)
TOP VIEW
|
Copyright
©
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Intersil Corporation 1999
CSO
VCC
DR
SDI
INTR
RST
TBRE
CO
RTS
DTR
DSR
CTS
GND
SDO
o
o
o
C to +125
C to +70
C to +85
o
o
o
C
C
C
5-1
Description
The Intersil 82C52 is a high performance programmable
Universal Asynchronous Receiver/Transmitter (UART) and
Baud Rate Generator (BRG) on a single chip. Utilizing the
Intersil advanced Scaled SAJI IV CMOS process, the 82C52
will support data rates up to 1M baud asynchronously with a
16X clock (16MHz clock frequency).
The on-chip Baud Rate Generator can be programmed for
any one of 72 different baud rates using a single industry
standard crystal or external frequency source. A unique pre-
scale divide circuit has been designed to provide standard
RS-232-C baud rates when using any one of three industry
standard crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).
A programmable buffered clock output (CO) is available and
can be programmed to provide either a buffered oscillator or
16X baud rate clock for general purpose system usage.
Ordering Information
PDIP
PLCC
CERDIP
CLCC
PACKAGE
SMD#
SMD#
D2
D3
D4
D5
D6
D7
A0
CMOS Serial Controller Interface
10
11
5
6
7
8
9
-55
-55
TEMPERATURE
-40
-40
-40
12
0
0
0
4
o
o
o
o
o
o
o
o
C to +70
C to +70
C to +70
RANGE
C to +125
C to +125
C to +85
C to +85
C to +85
82C52 (PLCC, CLCC)
13
3
14
TOP VIEW
2
o
o
o
o
o
o
C
C
C
o
o
C
C
C
C
C
15
1
82C52
CP82C52
IP82C52
CS82C52
IS82C52
CD82C52
ID82C52
MD82C52/B
8501501XA
MR82C52/B
85015013A
16
28
1M BAUD
17
27
File Number
18
26
25
24
23
22
21
20
19
E28.6
E28.6
N28.45
N28.45
F28.6
F28.6
F28.6
F28.6
J28.A
J28.A
PKG. NO.
SDI
INTR
RST
TBRE
CO
RTS
DTR
2950.1

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CD82C52 Summary of contents

Page 1

... TEMPERATURE RANGE 1M BAUD PKG. NO +70 C CP82C52 E28 - +85 C IP82C52 E28 +70 C CS82C52 N28. - +85 C IS82C52 N28. +70 C CD82C52 F28 - +85 C ID82C52 F28 - +125 C MD82C52/B F28.6 8501501XA F28 - +125 C MR82C52/B J28.A 85015013A J28.A 82C52 (PLCC, CLCC) TOP VIEW SDI 24 INTR ...

Page 2

Block Diagram DATA BUS D0-D7 BUFFER READ/WRITE WR CONTROL 11 A0 LOGIC CSO 13 IX PROGRAM- 14 MABLE OX BOUD RATE 21 CO GENERATOR 23 RST CONTROL LOGIC 24 INTR Pin ...

Page 3

Pin Description (Continued) PIN ACTIVE SYMBOL NO. TYPE LEVEL DSR 18 I Low DTR 19 O Low RTS 20 O Low TBRE 22 O High RST 23 I High INTR 24 O High SDI 25 I High ...

Page 4

Reset During and after power-up, the 82C52 Reset Input (RST) must be held high for at least two IX clock cycles in order to initialize and drive the 82C52 circuits to an idle mode until proper programming can be done. ...

Page 5

Baud Rate Select Register (BRSR) The 82C52 is designed to operate with a single crystal or external clock driving the IX input pin. The Baud Rate Select Register is used to select the divide ratio (one of 72) for the ...

Page 6

SDO output pin. The Receiver Enable bit gates off the input to the receiver circuitry when in the false state. Modem Interrupt Enable will permit any change in modem status line inputs (CTS, DSR) to cause an ...

Page 7

Parity Error (PE) Framing Error (FE) Overrun Error (OE) Received Break (RBRK) Modem Status (MS) Transmission Complete (TC) Transmitter Buffer Register Empty (TBRE) Data Ready (DR) FIGURE 5. USR Modem Status Register ...

Page 8

Bit 0, which corresponds the data bus, is always the first serial data bit transmitted. Provision is made for the transmitter parity to be the same or different from the receiver. The TBRE output pin and flag ...

Page 9

AD0, AD7 80C86 OR 80C88 INT CLK INTA 5MHz X1 CLK 2.5MHz 15MHz PCLK 15MHz X2 OSC 82C84A OR 82C85 FIGURE 11. 80C86/82C52 INTERFACE 82C52 CHIP SELECT CSO D0-D7 SDO 2 A0, A1 ADDRESS BUS SDI RD 82C88 IORD 82C52 ...

Page 10

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 11

AC Electrical Specifications V CC Timing Requirements and Responses SYMBOL PARAMETER (1) TSVCTL Select Setup to Control Leading Edge (2) TCTHSX Select Hold from Control Trailing Edge (3) TCTLCTH Control Pulse Width (4) TCTHCTL Control Disable to Control Enable (5) ...

Page 12

AC Testing Input, Output Waveforms INPUT V + 0. 0.4V IL FIGURE 12. PROPAGATION DELAY AC TESTING: All input signals (except IX and RST) must switch between V Timing Waveform CS0, A0, A1 (1) TSVCTL WR ...

Page 13

UART Timing Characterization All parameters listed in this table were laboratory bench characterized at room temperature on a small sample of parts. No guarantee is implied. The main intent here is to clarify functional operation of the 82C52. 82C52 UART ...

Page 14

UART Timing Characterization IX CO(IX) CO(BRG) CO(BRG) TDTX (18) TX DATA CO(BRG) 8 CO(BRG) PERIODS RX DATA START BIT RX BAUD COUNTER STARTS HERE INTERNAL SAMPLE 82C52 TCHCL (11) TCLCH (10) (15) TS1 (16) TS2 TCY (17) FIGURE 15. CLOCK ...

Page 15

UART Timing Characterization 8/I 9/I 10/I CO(BRG) WR (19) TWLTL NOTE 1 TBRE SDO RD INTR CO(BRG) (24) TCTHX NOTE 4 CTS TBRE LAST STOP BIT SDO NOTES: 1. TBRE bit D6 in USR is updated ...

Page 16

UART Timing Characterization 11 12 CO(BRG) SDI RD (25) TDRH DR NOTE 1 (21) TIHF NOTE 2 INTR MCR WR RTS/DTR RD DSR/CTS INTR NOTE 3 NOTES bit D7 in USR is updated each time DR changes state. ...

Page 17

Burn-In Circuits GND VCC NOTES 5.5V 0.5V CC GND = 4.5V 10% IH ...

Page 18

Die Characteristics DIE DIMENSIONS: 178.7 x 187 1mils METALLIZATION: Type: Silicon - Aluminum Å Å Thickness: 11k 2k Metallization Mask Layout 82C52 GLASSIVATION: Type: Nitrox ...

Page 19

... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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